1. Multioperand Addition Lecture 6

2. Required Reading Chapter 8, Multioperand Addition Note errata at: http://www.ece.ucsb.edu/~parhami/text_comp_arit_1ed.htm#errors Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design

3. Recommended Reading J-P. Deschamps, G. Bioul, G. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems Chapter 11.1.12 Multioperand Adders

4. Applications of multioperand addition Multiplication Inner product s =  x (i) y (i) =  i=0 n-1 i=0 n-1 p (i) p=a·x

5. Number of bits of the result S =  x (i) i=0 n-1 x (i)  [0..2 k -1] S max = n (2 k -1)S min = 0 # of bits of S = log 2 (S max + 1)= = log 2 (n (2 k -1) + 1)  log 2 n 2 k = = k + log 2 n

6. Serial implementation of multioperand addition

7. Adding 7 numbers in the binary tree of adders

8. Ripple-carry adders at levels i and i+1

9. Example: Adding 8 3-bit numbers

10. Ripple-Carry Carry Propagate Adder (CPA) a1a1 b1b1 FA c2c2 s1s1 a0a0 b0b0 c0c0 c1c1 s0s0 a2a2 b2b2 c3c3 s2s2 a n-1 b n-1 FA cncn s n-1 c n-1...

11. Carry Save Adder (CSA) FA c2c2 s1s1 a0a0 b0b0 c1c1 s0s0 c3c3 s2s2 cncn s n-1 c n-1... c0c0 s3s3 a1a1 b1b1 c1c1 a2a2 b2b2 c2c2 a n-1 b n-1 c n-1

12. A Ripple-Carry vs. Carry-Save Adder

13. 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 2424 2323 2 2121 2020 0 0 1 1 0 1 1 0 1 1 xyzxyz scsc Operation of a Carry Save Adder (CSA) Example x+y+z = s + c

14. Carry propagate and carry-save adders in dot notation

15. Specifying full- and half-adder blocks in dot notation

16. Carry-save adder for four operands x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 z 3 z 2 z 1 z 0 w 3 w 2 w 1 w 0 s 3 s 2 s 1 s 0 c 4 c 3 c 2 c 1 w 3 w 2 w 1 w 0 c 4 s 3 s 2 s 1 s 0 c 4 c 3 c 2 c 1 ’’’’ ’ ’ ’’ S 5 S 4 S 3 S 2 S 1 S 0

17. Carry-save adder for four operands s0s0 s1s1 s2s2 s3s3 c1c1 c2c2 c3c3 c4c4 s0s0 s1s1 s2s2 s3s3 c1c1 c2c2 c3c3 c4c4 ’ ’ ’ ’ ’ ’ ’ ’

18. x y z 4 4 4 CSA 4 w CPA sc s’ c’ S

19. Carry-save adder for six operands CSA tree Implementation of one-bit slice

20. Tree of carry save adders reducing seven numbers to two

21. Addition of seven six-bit numbers in dot notation

22. Adding seven k-bit numbers: block diagram

23. Relationship Between Number of Inputs and Tree Height

24. Latency Latency CSA = h(n)  T FA + Latency CPA (k, n) Tree height for n operands Widths CSA CPA k.. k + log 2 n typically close to k bits  k + log 2 n Component Adders Parameters of tree carry-save adders (1)

25. Maximum number of inputs that can be reduced to two by an h-level tree, n(h) Parameters of tree carry-save adders (2) n(0) = 2 n(h) = n(h-1) 3 2 n(1) = 3 n(2) = 4 n(3) = 6 n(4) = 9 n(5) = 13 n(6) = 19 2 ( ) h-1 < n(h)  2 ( ) h 3 2 3 2

26. Parameters of tree carry-save adders (3) Smallest height of the tree carry save adder for n operands, h(n) h(n) = 1 + h ( ) 2 3 n h(n)  log ( ) h(2) = 0 n 2 3 2

28. Wallace vs. Dadda Trees (1) Wallace trees Dadda trees Reduce the size of the final Carry Propagate Adder (CPA) Optimum from the point of view of speed Reduce the cost of the carry save tree Optimum (among the CSA trees) from the point of view of area

29. Wallace reduces number of operands at earliest opportunity –Goal of this is to have smallest number of bits for CPA adder –However, sometimes having a few bits longer CPA adder does not affect the propagation delay significantly (i.e. carry-lookahead) Dadda seeks to reduce the number of FA and HA units –May be at the cost of a slightly larger final CPA Wallace vs. Dadda Trees (2)

30. Wallace Tree

31. Dadda Tree

32. 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 2424 2323 2 2121 2020 0 1 1 1 0 0 1 1 0 0 1 0 0 1 1 abcdeabcde s0 s1 s2 5-to-3 Parallel Counter a+b+c+d+e = s0+s1+s2

33. Implementation of 1-bit of 5-to-3 parallel counter using single CLB slice of a Virtex FPGA

34. ww ww w w CSA CPA y=a+b+c+d+e mod 2 w abcde wwwww w PC CSA CPA y=a+b+c+d+e mod 2 w ab cde s2 s1 s0 Carry Save Adder vs. 5-to-3 Parallel Counter

35. Generalized Parallel Counters (5, 5; 4)-counter Fig. 8.17 Dot notation for a (5, 5; 4)-counter and the use of such counters for reducing five numbers to two numbers. Multicolumn reduction (2, 3; 3)-counter Unequal columns Generalized parallel counter = Parallel compressor