1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Adder structures Sebastian Kruse

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Types of adders Slide 2 Redundant Carry-Save (CSA) Redundant-Binary (RBA) Not redundant (CPA) Ripple-Carry (RCA), Manchester-Carry-Chain (MCC) Carry-Skip (CSK), Carry-Select (CSEL) Carry-Lookahead (CLA), Conditional-Sum (CSUM) Asynchronous adder

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Ripple-Carry adder Slide 3 Serialization of full adders Small area but slow speed In general the best adder for FPGA FPGA uses LUTs instead of AND, OR, XOR, NOT Optimized logic which speeds up RCA Delay time Area

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Carry-Skip adder Slide 4 CPA 0101 0101 Delay time Area

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Carry-Lookahead adder Slide 5 CLA-Block Delay time Area Fast adder with logarithm complexity but high area Idea: carry is calculated in advance Types of implementation (for carry generation) Slansky Kogge-Stone Brent-Kung Han-Carlson

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Brent-Kung Idea: use binary tree for carry propagation Two tree structures Carry collection Carry redistribution Slide 6 Delay time Area carry tree inverse carry tree

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Comparison on FPGA Slide 7 RCA Area : 103 Max. frequency : 431,779 MHz CSK Area : 125 Max. frequency : 384,025 MHz Brent Kung Area : 109 Max. frequency : 409,500 MHz

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Comparison on ASIC Slide 8 RCA Core size :4634,45 µm² Max. frequency : 3180 MHz P dyn : 22,154 mW P leak : 9,875 µW CSK Core size: 4324,63 µm² Max. frequency : 2910MHz P dyn : 18,651 mW P leak : 8,346 µW Brent Kung Core size : 4392,61 µm² Max. frequency : 2980 MHz P dyn : 19,406 mW P leak : 8,716 µW

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Thank you for your attention! Slide 9

10. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Half / full adder Slide 10 FA ab c in c out s HA ab c out s Half adder ((2,2)-counter) Full adder ((3,2)-counter)

11. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Comparison of adders Slide 11 0 1020 Number of bits 0 20 40 60 80 01020 Number of bits 0 0.2 0.4 Brent-Kung CSK RCA Brent-Kung RCA t p (nsec) Area (mm 2 ) Source: mountains.ece.umn.edu (2006) CSK

12. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Kogge-Stone Slide 12