Presentation is loading. Please wait.

Presentation is loading. Please wait.

Simplified Example of a LOCOS Fabrication Process

Published byRylie Wise Modified over 9 years ago

Similar presentations

Presentation on theme: "Simplified Example of a LOCOS Fabrication Process"— Presentation transcript:

1 Simplified Example of a LOCOS Fabrication Process
Prof. A. Mason Electrical and Computer Engineering Michigan State University LOCOS Fabrication Illustration Prof. A. Mason

2 LOCOS Defined LOCOS = LOCal Oxidation of Silicon
Defines a set of fabrication technologies where the wafer is masked to cover all active regions thick field oxide (FOX) is grown in all non-active regions Used for electrical isolation of CMOS devices Relatively simple to understand so often used to introduce/describe CMOS fabrication flows Not commonly used in modern fabrication other techniques, such as Shallow Trench Isolation (STI) are currently more common than LOCOS LOCOS Fabrication Illustration Prof. A. Mason

3 LOCOS –step 1 Form N-Well regions Grow oxide Deposit photoresist
NWELL mask photoresist oxide p-type substrate Cross section view NWELL mask Layout view LOCOS Fabrication Illustration Prof. A. Mason

4 LOCOS –step 1 Form N-Well regions Grow oxide Deposit photoresist
Pattern photoresist NWELL Mask expose only n-well areas NWELL mask photoresist oxide p-type substrate Cross section view NWELL mask Layout view LOCOS Fabrication Illustration Prof. A. Mason

5 LOCOS –step 1 Form N-Well regions Grow oxide Deposit photoresist
Pattern photoresist NWELL Mask expose only n-well areas Etch oxide Remove photresist oxide p-type substrate Cross section view Layout view LOCOS Fabrication Illustration Prof. A. Mason

6 LOCOS –step 1 Form N-Well regions Grow oxide Deposit photoresist
Pattern photoresist NWELL Mask expose only n-well areas Etch oxide Remove photoresist Diffuse n-type dopants through oxide mask layer n-well p-type substrate Cross section view Layout view LOCOS Fabrication Illustration Prof. A. Mason

7 LOCOS –step 2 Form Active Regions Deposit SiN over wafer
Deposit photoresist over SiN layer ACTIVE mask n-well photoresist SiN p-type substrate ACTIVE mask LOCOS Fabrication Illustration Prof. A. Mason

8 LOCOS –step 2 Form Active Regions Deposit SiN over wafer
Deposit photoresist over SiN layer Pattern photoresist *ACTIVE MASK ACTIVE mask n-well photoresist SiN p-type substrate ACTIVE mask LOCOS Fabrication Illustration Prof. A. Mason

9 LOCOS –step 2 Form Active Regions Deposit SiN over wafer
Deposit photoresist over SiN layer Pattern photoresist *ACTIVE MASK Etch SiN in exposed areas leaves SiN mask which blocks oxide growth n-well photoresist SiN p-type substrate ACTIVE mask LOCOS Fabrication Illustration Prof. A. Mason

10 LOCOS –step 2 Form Active Regions Deposit SiN over wafer
Deposit photoresist over SiN layer Pattern photoresist *ACTIVE MASK Etch SiN in exposed areas leaves SiN mask which blocks oxide growth Remove photoresist Grow Field Oxide (FOX) thermal oxidation n-well FOX p-type substrate ACTIVE mask LOCOS Fabrication Illustration Prof. A. Mason

11 LOCOS –step 2 Form Active Regions Deposit SiN over wafer
Deposit photoresist over SiN layer Pattern photoresist *ACTIVE MASK Etch SiN in exposed areas leaves SiN mask which blocks oxide growth Remove photoresist Grow Field Oxide (FOX) thermal oxidation Remove SiN n-well FOX p-type substrate ACTIVE mask LOCOS Fabrication Illustration Prof. A. Mason

12 LOCOS –step 3 Form Gate (Poly layer) Grow thin Gate Oxide
over entire wafer negligible effect on FOX regions gate oxide LOCOS Fabrication Illustration Prof. A. Mason

13 LOCOS –step 3 Form Gate (Poly layer) Grow thin Gate Oxide
over entire wafer negligible effect on FOX regions Deposit Polysilicon Deposit Photoresist POLY mask polysilicon gate oxide POLY mask LOCOS Fabrication Illustration Prof. A. Mason

14 LOCOS –step 3 Form Gate (Poly layer) Grow thin Gate Oxide
over entire wafer negligible effect on FOX regions Deposit Polysilicon Deposit Photoresist Pattern Photoresist *POLY MASK Etch Poly in exposed areas Etch/remove Oxide gate protected by poly POLY mask gate oxide POLY mask LOCOS Fabrication Illustration Prof. A. Mason

15 LOCOS –step 3 Form Gate (Poly layer) Grow thin Gate Oxide
over entire wafer negligible effect on FOX regions Deposit Polysilicon Deposit Photoresist Pattern Photoresist *POLY MASK Etch Poly in exposed areas Etch/remove Oxide gate protected by poly gate oxide LOCOS Fabrication Illustration Prof. A. Mason

16 LOCOS –step 4 Form pmos S/D Cover with photoresist PSELECT mask
LOCOS Fabrication Illustration Prof. A. Mason

17 LOCOS –step 4 Form pmos S/D Cover with photoresist Pattern photoresist
*PSELECT MASK PSELECT mask POLY mask LOCOS Fabrication Illustration Prof. A. Mason

18 LOCOS –step 4 Form pmos S/D Cover with photoresist Pattern photoresist
*PSELECT MASK Implant p-type dopants Remove photoresist p+ dopant p+ dopant POLY mask LOCOS Fabrication Illustration Prof. A. Mason

19 LOCOS –step 5 Form nmos S/D Cover with photoresist NSELECT mask
POLY mask LOCOS Fabrication Illustration Prof. A. Mason

20 LOCOS –step 5 Form nmos S/D Cover with photoresist Pattern photoresist
*NSELECT MASK NSELECT mask p+ p+ p+ n POLY mask LOCOS Fabrication Illustration Prof. A. Mason

21 LOCOS –step 5 Form nmos S/D Cover with photoresist Pattern photoresist
*NSELECT MASK Implant n-type dopants Remove photoresist n+ n+ n+ p+ p+ p+ n n+ dopant n+ dopant POLY mask LOCOS Fabrication Illustration Prof. A. Mason

22 LOCOS –step 6 Form Contacts Deposit oxide Deposit photoresist
CONTACT mask Form Contacts Deposit oxide Deposit photoresist n+ n+ n+ p+ p+ p+ n CONTACT mask LOCOS Fabrication Illustration Prof. A. Mason

23 LOCOS –step 6 Form Contacts Deposit oxide Deposit photoresist
CONTACT mask Form Contacts Deposit oxide Deposit photoresist Pattern photoresist *CONTACT Mask One mask for both active and poly contact shown n+ n+ n+ p+ p+ p+ n CONTACT mask LOCOS Fabrication Illustration Prof. A. Mason

24 LOCOS –step 6 Form Contacts Deposit oxide Deposit photoresist
Pattern photoresist *CONTACT Mask One mask for both active and poly contact shown Etch oxide n+ n+ n+ p+ p+ p+ n LOCOS Fabrication Illustration Prof. A. Mason

25 LOCOS –step 6 Form Contacts Deposit oxide Deposit photoresist
Pattern photoresist *CONTACT Mask One mask for both active and poly contact shown Etch oxide Remove photoresist Deposit metal1 immediately after opening contacts so no native oxide grows in contacts Planerize make top level n+ n+ n+ p+ p+ p+ n LOCOS Fabrication Illustration Prof. A. Mason

26 LOCOS –step 7 Form Metal 1 Traces Deposit photoresist METAL1 mask
n+ n+ n+ p+ p+ p+ n METAL1 mask LOCOS Fabrication Illustration Prof. A. Mason

27 LOCOS –step 7 Form Metal 1 Traces Deposit photoresist
METAL1 mask Form Metal 1 Traces Deposit photoresist Pattern photoresist *METAL1 Mask n+ n+ n+ p+ p+ p+ n METAL1 mask LOCOS Fabrication Illustration Prof. A. Mason

28 LOCOS –step 7 Form Metal 1 Traces Deposit photoresist
Pattern photoresist *METAL1 Mask Etch metal n+ n+ n+ p+ p+ p+ n metal over poly outside of cross section LOCOS Fabrication Illustration Prof. A. Mason

29 LOCOS –step 7 Form Metal 1 Traces Deposit photoresist
Pattern photoresist *METAL1 Mask Etch metal Remove photoresist n+ n+ n+ p+ p+ p+ n LOCOS Fabrication Illustration Prof. A. Mason

30 LOCOS –step 8 Form Vias to Metal1 Deposit oxide Planerize oxide
VIA mask Form Vias to Metal1 Deposit oxide Planerize oxide Deposit photoresist n+ n+ n+ p+ p+ p+ n VIA mask LOCOS Fabrication Illustration Prof. A. Mason

31 LOCOS –step 8 Form Vias to Metal1 Deposit oxide Planerize
VIA mask Form Vias to Metal1 Deposit oxide Planerize Deposit photoresist Pattern photoresist *VIA Mask n+ n+ n+ p+ p+ p+ n VIA mask LOCOS Fabrication Illustration Prof. A. Mason

32 LOCOS –step 8 Form Vias to Metal1 Deposit oxide Planerize
Deposit photoresist Pattern photoresist *VIA Mask Etch oxide Remove photoresist n+ n+ n+ p+ p+ p+ n LOCOS Fabrication Illustration Prof. A. Mason

33 LOCOS –step 8 Form Vias to Metal1 Deposit oxide Planerize
Deposit photoresist Pattern photoresist *VIA Mask Etch oxide Remove photoresist Deposit Metal2 n+ n+ n+ p+ p+ p+ n LOCOS Fabrication Illustration Prof. A. Mason

34 LOCOS –step 9 Form Metal2 Traces Deposit photoresist METAL2 mask
n+ n+ n+ p+ p+ p+ n METAL2 mask LOCOS Fabrication Illustration Prof. A. Mason

35 LOCOS –step 9 Form Metal2 Traces Deposit photoresist
METAL2 mask Form Metal2 Traces Deposit photoresist Pattern photoresist *METAL2 Mask n+ n+ n+ p+ p+ p+ n METAL2 mask LOCOS Fabrication Illustration Prof. A. Mason

36 LOCOS –step 9 Form Metal2 Traces Deposit photoresist
Pattern photoresist *METAL2 Mask Etch metal n+ n+ n+ p+ p+ p+ n LOCOS Fabrication Illustration Prof. A. Mason

37 LOCOS –step 9 Form Metal2 Traces Deposit photoresist
Pattern photoresist *METAL2 Mask Etch metal Remove photoresist n+ n+ n+ p+ p+ p+ n LOCOS Fabrication Illustration Prof. A. Mason

38 LOCOS –step 10+ Form Additional Traces Deposit oxide
Deposit photoresist Pattern photoresist Etch oxide Deposit metal Deposit photresist Etch metal Repeat for each additional metal n+ n+ n+ p+ p+ p+ n p-type substrate LOCOS Fabrication Illustration Prof. A. Mason

39 Simplifications from complete process
skipped several substrate doping steps channel implant to adjust threshold voltages surface implant to increase breakdown voltage no LDD, lightly-doped drain no deposition of contact interface materials metal patterning simplified more complex “lift-off” process often used no overglass (thick top dielectric) layer no bonding pad layer simplified use of dark/clear field masks and positive/negative photoresist LOCOS Fabrication Illustration Prof. A. Mason

Download ppt "Simplified Example of a LOCOS Fabrication Process"

Similar presentations

CMOS Fabrication EMT 251.

CMOS Fabrication EMT 251.
Lecture 0: Introduction

Lecture 0: Introduction
CMOS Inverter Layout P-well mask (dark field) Active (clear field)

CMOS Inverter Layout P-well mask (dark field) Active (clear field)
CMOS Process at a Glance

CMOS Process at a Glance
Analog VLSI Design Nguyen Cao Qui.

Analog VLSI Design Nguyen Cao Qui.
VLSI Design Lecture 2: Basic Fabrication Steps and Layout

VLSI Design Lecture 2: Basic Fabrication Steps and Layout

A Primer on CMOS Technology. Objectives: 1.To Introduce about CMOS technology.

A Primer on CMOS Technology. Objectives: 1.To Introduce about CMOS technology.
Lecture 11: MOS Transistor

Lecture 11: MOS Transistor
Introduction to CMOS VLSI Design Lecture 0: Introduction

Introduction to CMOS VLSI Design Lecture 0: Introduction
Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.

Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.
School of Microelectronic Engineering EMT362: Microelectronic Fabrication CMOS ISOLATION TECHNOLOGY Part 2 Ramzan Mat Ayub School of Microelectronic Engineering.

School of Microelectronic Engineering EMT362: Microelectronic Fabrication CMOS ISOLATION TECHNOLOGY Part 2 Ramzan Mat Ayub School of Microelectronic Engineering.
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,
Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.

Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.
Introduction to CMOS VLSI Design Lecture 0: Introduction

Introduction to CMOS VLSI Design Lecture 0: Introduction
Paulo MoreiraTechnology1 Outline Introduction – “Is there a limit ?” Transistors – “CMOS building blocks” Parasitics I – “The [un]desirables” Parasitics.

Paulo MoreiraTechnology1 Outline Introduction – “Is there a limit ?” Transistors – “CMOS building blocks” Parasitics I – “The [un]desirables” Parasitics.
Device Fabrication Example

Device Fabrication Example
Introduction Integrated circuits: many transistors on one chip.

Introduction Integrated circuits: many transistors on one chip.
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

Similar presentations

Ads by Google