1. EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Digital Integrated Circuits A Design Perspective Manufacturing Process July 30, 2002

2. EE141 © Digital Integrated Circuits 2nd Manufacturing 2 CMOS Process

3. EE141 © Digital Integrated Circuits 2nd Manufacturing 3 A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process

4. EE141 © Digital Integrated Circuits 2nd Manufacturing 4 Circuit Under Design & Layout View

5. EE141 © Digital Integrated Circuits 2nd Manufacturing 5 oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process

6. EE141 © Digital Integrated Circuits 2nd Manufacturing 6 Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

7. EE141 © Digital Integrated Circuits 2nd Manufacturing 7 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers

8. EE141 © Digital Integrated Circuits 2nd Manufacturing 8 CMOS Process Walk-Through p + p-epi (a) Base material: p+ substrate with p-epi layer p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask p + p-epi SiO 2 3 SiN 4 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)

9. EE141 © Digital Integrated Circuits 2nd Manufacturing 9 CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride (e) After n-well and V Tp adjust implants n (f) After p-well and V Tn adjust implants p

10. EE141 © Digital Integrated Circuits 2nd Manufacturing 10 CMOS Process Walk-Through (g) After polysilicon deposition and etch poly(silicon)

11. EE141 © Digital Integrated Circuits 2nd Manufacturing 11 CMOS Process Walk-Through

12. EE141 © Digital Integrated Circuits 2nd Manufacturing 12 Advanced Metallization  Introduced by IBM  Filling trench, then polishing

13. EE141 © Digital Integrated Circuits 2nd Manufacturing 13 Design Rules

14. EE141 © Digital Integrated Circuits 2nd Manufacturing 14 3D Perspective Polysilicon Aluminum

15. EE141 © Digital Integrated Circuits 2nd Manufacturing 15 Design Rules  Interface between designer and process engineer  Guidelines for constructing process masks  Unit dimension: Minimum line width  scalable design rules: lambda parameter  absolute dimensions (micron rules)

16. EE141 © Digital Integrated Circuits 2nd Manufacturing 16 CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Black Select (p+,n+) Green

17. EE141 © Digital Integrated Circuits 2nd Manufacturing 17 Layers in 0.25  m CMOS process

18. EE141 © Digital Integrated Circuits 2nd Manufacturing 18 Intra-Layer Design Rules Metal2 4 3

19. EE141 © Digital Integrated Circuits 2nd Manufacturing 19 Transistor Layout

20. EE141 © Digital Integrated Circuits 2nd Manufacturing 20 Vias and Contacts

21. EE141 © Digital Integrated Circuits 2nd Manufacturing 21 CMOS Inverter Layout

22. EE141 © Digital Integrated Circuits 2nd Manufacturing 22 Layout Editor

23. EE141 © Digital Integrated Circuits 2nd Manufacturing 23 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.

24. EE141 © Digital Integrated Circuits 2nd Manufacturing 24 Sticks Diagram 1 3 In Out V DD GND Stick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by “compaction” program

25. EE141 © Digital Integrated Circuits 2nd Manufacturing 25 Packaging

26. EE141 © Digital Integrated Circuits 2nd Manufacturing 26 Packaging Requirements  Electrical: Low parasitics  Mechanical: Reliable and robust  Thermal: Efficient heat removal  Economical: Cheap

27. EE141 © Digital Integrated Circuits 2nd Manufacturing 27 Die-to-Package: Wire Bonding

28. EE141 © Digital Integrated Circuits 2nd Manufacturing 28 Die-to-Package: Tape-Automated Bonding (TAB)

29. EE141 © Digital Integrated Circuits 2nd Manufacturing 29 Die-to-Package: Flip-Chip Bonding

30. EE141 © Digital Integrated Circuits 2nd Manufacturing 30 Package-to-Board

31. EE141 © Digital Integrated Circuits 2nd Manufacturing 31 Package Types  Bare die  DIP  PGA  Small-outline IC  QFP  PLCC (J-shaped)  Leadless carrier

32. EE141 © Digital Integrated Circuits 2nd Manufacturing 32 Package Parameters

33. EE141 © Digital Integrated Circuits 2nd Manufacturing 33 Multi-Chip Modules  R, C, L parasitic reduced  But, cost increased