1. Titre : Développement de circuits logiques programmables résistants aux aléas logiques en technologie CMOS submicrométrique Titre anglais : Development of Single Event Upset hardened programmable logic devices in deep submicron CMOS Sandro Bonacini

2. Outline Motivation and objectives Motivation and objectives CERN and the LHC CERN and the LHC Radiation environment at the LHC Radiation environment at the LHC Radiation effects on ICs Radiation effects on ICs Total Ionizing Dose (TID) effects and hardening Total Ionizing Dose (TID) effects and hardening Single Event Effects (SEE) Single Event Effects (SEE) Study on SEU hardening techniques Study on SEU hardening techniques Design of SEU-robust registers Design of SEU-robust registers Experimental results Experimental results Design of a radiation-tolerant FPGA Design of a radiation-tolerant FPGA Study on FPGA architectures Study on FPGA architectures Experimental results Experimental results Design of a radiation-tolerant PLD Design of a radiation-tolerant PLD

3. Motivation Experimental High-Energy Physics (HEP) would benefit from the availability of radiation-hard programmable logic Experimental High-Energy Physics (HEP) would benefit from the availability of radiation-hard programmable logic FPGAs FPGAs Fast design development Flexibility (changing requirements, failure recovery, …) Possible use as IP-core PLDs Glue logic, simple state machines Hard fixes in the late stages of a project Commercial devices do not attain radiation levels of inner sub-detectors in LHC’s experiments

4. Objectives Programmable logic components Programmable logic components TID-tolerant to experiment upgrades inner tracker levels TID-tolerant to experiment upgrades inner tracker levels Built-in SEU hardness Built-in SEU hardness Configuration bank and user registers… Configuration bank and user registers… User can avoid utilization of SEU hardening techniques at HDL level and/or reconfiguration techniques for program restoration User can avoid utilization of SEU hardening techniques at HDL level and/or reconfiguration techniques for program restoration FPGA FPGA SRAM-based, ~25k gates, 256 I/Os SRAM-based, ~25k gates, 256 I/Os in 0.13μm CMOS in 0.13μm CMOS PLD PLD Fuse-based, 10 inputs, 8 bidirectional Fuse-based, 10 inputs, 8 bidirectional in 0.25μm CMOS in 0.25μm CMOS

5. CERN is a particle physics research laboratory run by 20 member states CERN is a particle physics research laboratory run by 20 member states Currently a new accelerator is being assembled at CERN Currently a new accelerator is being assembled at CERN the Large Hadron Collider the Large Hadron Collider … whose target is to accelerate protons to an energy of 7 TeV … whose target is to accelerate protons to an energy of 7 TeV CERN and the Large Hadron Collider (LHC)

6. Experiments at LHC LHC’s beam pipe runs on a 27-km- long underground tunnel LHC’s beam pipe runs on a 27-km- long underground tunnel Four experiments are based on the LHC and are currently being built Four experiments are based on the LHC and are currently being built The experiments are located around the proton-proton collision points The experiments are located around the proton-proton collision points Grenoble

7. Example of an LHC experiment: the Compact Muon Solenoid Experiments at the LHC have a considerable size Experiments at the LHC have a considerable size Several stories high, tens of meters long Composed by several sub- detectors Cover ~all directions from interaction point People standing in superconducting coil at 100K

8. Fluence of hadrons in CMS inner sub-detectors At peak luminosity, up to 10 15 cm -2 hadrons in 10 years of operation At peak luminosity, up to 10 15 cm -2 hadrons in 10 years of operation Simulations performed with FLUKA Simulations performed with FLUKA 7.3 m >3.2 · 10 14 >10 14 >10 15 >3.2 · 10 13 >10 13 >3.2 · 10 12 >10 12 >3.2 · 10 11 >10 11 3.2 · 10 14 > 10 14 > 10 15 > 3.2 · 10 13 > 10 13 > 3.2 · 10 12 > 10 12 > 3.2 · 10 11 > 10 11 > Fluence of neutrons (>100keV) and charged hadrons in cm –2 2.6 m 5.2 m

9. Total Ionizing Dose in CMS inner sub-detectors Up to 35 Mrad in 10 years of operation at peak luminosity Up to 35 Mrad in 10 years of operation at peak luminosity Dose rate up to 1.5 krad/h Dose rate up to 1.5 krad/h >10 7 >10 6 >10 5 >10 4 >10 3 >10 2 10 7 > 10 6 > 10 5 > 10 4 > 10 3 > 10 2 > Radiation total dose in rad 7.3 m 2.6 m 5.2 m

10. Total dose effects on MOS transistors and solutions In order avoid these conductive paths it is possible to use (in nMOS transistors) In order avoid these conductive paths it is possible to use (in nMOS transistors) Enclosed Layout Transistors Enclosed Layout Transistors p+ guard rings p+ guard rings TID induces Threshold voltage shift Minor issue in deep submicron devices Leakage current increase in nMOS due to the accumulation of positive charge in the field oxide which induces conductive paths in the substrate

11. ELT vs linear transistors 0.25 micron 0.13 micron Leakage current Threshold voltage shift

12. Total Ionizing Dose hardening Design practices for TID hardening Design practices for TID hardening 0.25μm CMOS technology 0.25μm CMOS technology Enclosed Layout Transistors Enclosed Layout Transistors Guard-rings Guard-rings 0.13μm CMOS technology 0.13μm CMOS technology Sufficiently TID-hard for digital logic without ELT Sufficiently TID-hard for digital logic without ELT Faccio and Cervelli, “Radiation-induced edge effects in deep submicron CMOS transistors”, IEEE Transactions on Nuclear Science, vol. 52, December 2005 Use of linear transistors with W>0.30μm Use of linear transistors with W>0.30μm O.25 micron O.13 micron

13. Single-Event Effects (SEEs) Effects due to a single ionizing particle crossing the device Effects due to a single ionizing particle crossing the device Single-Event Latchup Single-Event Latchup destructive effect which can occur because of the parasitic thyristor formed by the junction structure present in CMOS ICs destructive effect which can occur because of the parasitic thyristor formed by the junction structure present in CMOS ICs Deep submicron technologies are becoming less susceptible (low supply voltage, highly doped substrate, trench isolation between wells, …) Deep submicron technologies are becoming less susceptible (low supply voltage, highly doped substrate, trench isolation between wells, …) Single-Event Upset Single-Event Upset Non-destructive effect which alters the data stored in a memory circuit by deposition of charge in the circuit nodes Non-destructive effect which alters the data stored in a memory circuit by deposition of charge in the circuit nodes … gate rupture, snapback, burnout … … gate rupture, snapback, burnout …

14. Single-Event Upsets (SEUs) An ionizing particle creates electron-hole pairs which are collected by the electric field of junctions An ionizing particle creates electron-hole pairs which are collected by the electric field of junctions The voltage on the node connected to the junction changes The voltage on the node connected to the junction changes In a typical SRAM cell if 1 of the 2 memory nodes is brought above/below Vdd/2 the stored value is corrupted

15. Single-Event Transients (SETs) SEUs can also be generated indirectly by a particle hit in the combinatorial logic which creates a transient pulse propagating through the datapath SEUs can also be generated indirectly by a particle hit in the combinatorial logic which creates a transient pulse propagating through the datapath If the pulse reaches the FF during the closing edge of the clock the data is corrupted If the pulse reaches the FF during the closing edge of the clock the data is corrupted SET-induced-SEU rate is proportional to clock frequency SET-induced-SEU rate is proportional to clock frequency 1

16. Study on SEU hardening Several ways to protect memories against SEUs Several ways to protect memories against SEUs System-level techniques System-level techniques Triple Module Redundancy (TMR) Triple Module Redundancy (TMR) Error Correction Coding (ECC) Error Correction Coding (ECC) Circuit-level techniques Circuit-level techniques Dual-Interlocked Cell Dual-Interlocked Cell Whitaker cell Whitaker cell Dooley, Rocket, SERT, … Dooley, Rocket, SERT, … Device-level techniques Device-level techniques Capacitance increase, threshold voltage control, … Capacitance increase, threshold voltage control, …

17. Hamming Encoding Tolerates 1 error over n bit Tolerates 1 error over n bit Efficient coding Efficient coding log 2 (n + 1) additive bits on n-bit codewords Encoder/decoder is necessary Encoder/decoder is necessary Logic complexity grows as O(nlogn) Logic complexity grows as O(nlogn) Suitable for big RAM blocks Suitable for big RAM blocks 1 enc/dec for a whole memory 1 enc/dec for a whole memory Needs refresh routine Needs refresh routine Not suitable for FPGAs Not suitable for FPGAs All data must be accessible at all times… All data must be accessible at all times… … would need huge enc/dec … would need huge enc/dec Difficult implementation of protection against SETs Difficult implementation of protection against SETs Registers Encoder Decoder Combinatorial logic

18. Triple Module Redundancy Triplicate registers and use a majority voter to decode Better protection than ECC Tolerates 1 error over 3 bit Less efficient than ECC 3x area and power Protection against SETs Redundant combinatorial logic Suitable for high-speed applications

19. Dual-Interlocked Cell (DICE) 4 memory nodes 4 memory nodes Each memory node is correlated to 2 other memory nodes Each memory node is correlated to 2 other memory nodes Interlock Interlock Symmetric cell Symmetric cell Each node is equivalent to the others Each node is equivalent to the others 2 stable states 2 stable states (1,0,1,0) (1,0,1,0) (0,1,0,1) (0,1,0,1) pMOS propagate right only low values pMOS propagate right only low values nMOS propagate left only high values nMOS propagate left only high values T. Calin, M. Nicolaidis & R. Velazco. “Upset Hardened Memory Design for Submicron CMOS Technology”. IEEE Transactions on Nuclear Science, vol. 43, no. 6, pages 2874-2878, December 1996. Intrinsically immune to single-node particle hits Vulnerable to multiple-node particle hits 1100 1 - 1z 0z A BCD

20. Choice for SEU hardening: DICE Using a SEU-robust register circuit gives the best trade-off between area occupancy and SEU tolerance Using a SEU-robust register circuit gives the best trade-off between area occupancy and SEU tolerance The DICE is the smallest SEU-robust cell The DICE is the smallest SEU-robust cell 12 transistors per memory cell 12 transistors per memory cell 2x with respect to a traditional SRAM cell 2x with respect to a traditional SRAM cell Smaller area than TMR (3x) Smaller area than TMR (3x) Better protection than ECC Better protection than ECC AB CD

21. SEU-robust latch …add clock driven transmission gates to access memory nodes… Fully 2 redundant Fully 2× redundant 2 inputs 2 inputs 2 outputs 2 outputs 2 clock buffers 2 clock buffers Normally they have the same logic levels Normally they have the same logic levels Q0 Q1 ck0 ck1 ck0n ck1n ck1 ck1n ck0 ck0n D0 D1 A BCD AB CD

22. Register layout for SEU robustness SEU-register is composed by a master latch and a slave latch SEU-register is composed by a master latch and a slave latch Master nodes: MA, MB, MC, MD Master nodes: MA, MB, MC, MD Slave nodes: SA, SB, SC, SD Slave nodes: SA, SB, SC, SD Latch is vulnerable to multiple-node particle hits on correlated nodes Latch is vulnerable to multiple-node particle hits on correlated nodes The nodes of the two latches are interleaved in order to increase the distance between correlated nodes The nodes of the two latches are interleaved in order to increase the distance between correlated nodes Less probability of multiple-node particle hit Less probability of multiple-node particle hit SA & output buffer clock buffer MBSB clock buffer MA SC & output buffer clock buffer MDSD clock buffer MC

23. SET protection: duplicated logic Duplicate combinatorial logic Duplicate combinatorial logic Use SEU-robust FF Use SEU-robust FF SEU-robust FF has 2 inputs and 2 outputs SEU-robust FF has 2 inputs and 2 outputs Can tolerate an SEU on one of the two inputs. Can tolerate an SEU on one of the two inputs. Duplicate data path alleviates the problem of latching erroneous states Duplicate data path alleviates the problem of latching erroneous states SEU-R FF SEU-R FF Combinatorial Logic SEU-R FF Combinatorial Logic FF Combinatorial Logic FF Protection against Single-Event Transients (SETs) Which occur in combinatorial logic and propagate to the flip-flops Non SET-robust SET-robust

24. Heavy-ion beam tests on SEU-robust register Static shift-register test Static shift-register test Stream in configuration Stream in configuration Beam start/stop Beam start/stop Retrieve configuration & compare Retrieve configuration & compare Dynamic shift-register test Dynamic shift-register test Continuous configuration load, retrieve & compare while configuration clock is running and beam is on Continuous configuration load, retrieve & compare while configuration clock is running and beam is on Two test chips were fabricated 0.25μm CMOS 2×2 mm 2, 1024 SEU-robust registers 0.13μm CMOS 1×2 mm 2, 9216 SEU-robust registers, 4096 standard library registers Test controller USB interface Device Under Test (back)

25. Test chip in 0.25μm CMOS Test results: Test results: SEU robustness of the register cell up to an LET of 79.6 cm 2 MeV/mg no errors observed in either static and dynamic test modes At an LET of 112 cm 2 MeV/mg and only in the dynamic test mode, the register cell showed SEU sensitivity, with SEU cross-section of 6.2·10 -10 cm 2 /bit LHC environment: LET up to 17 cm 2 MeV/mg Huhtinen and Faccio, “Computational method to estimate Single Event Upset rates in an accelerator environment”, Nuclear Instruments and Methods in Physics Research A 450 (2000) 155-172 For comparison: standard cell flip-flop in same technology has LET th = σ sat For comparison: standard cell flip-flop in same technology has LET th =14.7cm 2 MeV/mg and σ sat =2.59·10 -7 cm 2 /bit

26. Test chip in 0.13μm CMOS 0.13μm CMOS 0.13μm CMOS Good static mode robustness Good static mode robustness no errors up to 45.8 no errors up to 45.8 cm 2 MeV/mg In dynamic mode register shows sensitivity In dynamic mode register shows sensitivity strongly dependent on angle of incidence of the beam strongly dependent on angle of incidence of the beam Suitable as configuration register Suitable as configuration register Not suitable as user register Not suitable as user register

27. Comparison of SEU-robust registers in 0.25μm and 0.13μm CMOS Feature size [μm] 0.250.13 μm Cell size [μm 2 ]68×1114.5×3.6 Core power supply voltage [V]2.51.2 Distance between memory nodes [μm] 102.4 Number of metal levels used23 Enclosed layout transistorsyesno [μm] Minimum device width [μm]3.230.30 Typical inverter input capacitance [fF]251 Drain area [ Drain area [cm 2 ] ≥5.8 ≥5.8·10 -9 ≥1.2 ≥1.2·10 -9 Static test cross-section [] @LET ~34 Static test cross-section [cm 2 /bit] @LET ~34cm 2 MeV/mg ≤1 ≤1.5· 10 -9 ≤1 ≤1.5· 10 -10 Dynamic test LET [ @σ~ Dynamic test LET [cm 2 MeV/mg] @σ~6.7·10 -10 cm 2 /bit 11232.4

28. Study on FPGA architectures FPGAs differ on FPGAs differ on Granularity Granularity size and implementation capability of the Logic Block (LB) size and implementation capability of the Logic Block (LB) Routing structure Routing structure Island-style Island-style Sea-of-gates Sea-of-gates I/O signaling capabilities I/O signaling capabilities Programming technique Programming technique SRAM, fuses, Flash, … SRAM, fuses, Flash, … Special-purpose blocks Special-purpose blocks Multipliers, block RAM, PLL/DLLs, processor cores, … Multipliers, block RAM, PLL/DLLs, processor cores, …

29. Logic Block Best granularity 4-input-1-output Look-Up Table (LUT) implements any boolean function of 4 variables holds its truth table in 16 configuration registers can also be used as a 16×1- bit RAM block 31 configuration bits per LB are present and are organized in a shift-register structure 4-input LUT Carry chain A[0] A[1] A[2] A[3] COUT Y YQ SEU-R FF S/R CIN CLK D

30. Programmable interconnections Hierarchical routing LB has 17 I/Os 18 wires per direction 6 long lines 12 short-distance lines 8 direct neighbor connections 8 direct neighbor connections Connections implemented with tristate buffers transmission gates multiplexers 256 configuration registers in total 256 configuration registers in total

31. Radiation-tolerant FPGA Typical FPGA architecture Typical FPGA architecture Array of 3232 Logic Blocks (LBs) Array of 32×32 Logic Blocks (LBs) Configurable routing Configurable routing SRAM based SRAM based Reprogrammable Reprogrammable 256 I/Os 256 I/Os ~25k equivalent gates ~25k equivalent gates 2560 total user F/Fs 2560 total user F/Fs Possible use as IP-core Possible use as IP-core Logic block

32. Test chip for Logic Block A test chip was fabricated in 0.25 micron CMOS A test chip was fabricated in 0.25 micron CMOS Containing 32 LBs organized in 4 modules Containing 32 LBs organized in 4 modules No programmable interconnections No programmable interconnections Hardwired connections Hardwired connections Cascaded LBs Cascaded LBs SEU/SET testing performed SEU/SET testing performed Heavy-ion beam Heavy-ion beam All LBs configured as 4-way registered XOR All LBs configured as 4-way registered XOR Clocked at 25 MHz Clocked at 25 MHz Pseudo-random data input Pseudo-random data input No errors observed No errors observed σ ≤ 9 σ ≤ 9.4·10 -8 cm 2 /bit

33. Radiation-tolerant PLD Compatible with 16LV8 commercial device Compatible with 16LV8 commercial device Fuse based Fuse based Laser programmable Laser programmable 10 inputs, 8 programmable input/outputs 10 inputs, 8 programmable input/outputs Configurable AND matrix generates minterms Configurable AND matrix generates minterms Fixed OR matrix sums minterms Fixed OR matrix sums minterms 8 minterms per output 8 minterms per output Outputs can be registered or not Outputs can be registered or not Outputs are fed back to AND matrix for generation of more complex functions Outputs are fed back to AND matrix for generation of more complex functions

34. Fuses & PLD chip layout Fuses consist in a 71 μm 2 metal line (aluminum) Fuses consist in a 7×1 μm 2 metal line (aluminum) Laser programmable Laser programmable 2080 programming fuses 2080 programming fuses Occupy 70% of core area Occupy 70% of core area Chip size is 22 mm 2 Chip size is 2×2 mm 2 laser

35. Conclusions An SEU-robust register structure was designed and tested in two CMOS technologies Results obtained in the 0.25 μm technology demonstrate the register is suitable for the implementation of programmable logic The 0.13 μm circuit showed good robustness in the static tests but appeared to be sensitive in the dynamic tests Suitable for configuration storage Additional work is necessary for the FPGA user register The approach demonstrated the feasibility of the SEU-tolerant radiation-hard PLD and FPGA PLD chip was fabricated and tested The LB of the FPGA design was finalized, work is on going to complete the FPGA with interconnection infrastructure