1. NCHUCS1 Scan Chain Reorder Sying-Jyan Wang Department of Computer Science National Chung-Hsing University

2. NCHUCS2 Outline  Overview  Scan chain order: does it matter?  Cluster-based reordering for low- power BIST  Experimental results  Future work

3. NCHUCS3 Outline ■ Overview  Scan chain order: does it matter?  Cluster-based reordering for low- power BIST  Experimental results  Future work

4. NCHUCS4 Digital Testing  To detect manufacturing defects  Apply test patterns and observe output responses  Test patterns generated for targeted fault models

5. NCHUCS5 Scenario for Manufacture Test TEST VECTORS MANUFACTURED CIRCUIT COMPARATOR CIRCUIT RESPONSE PASS/FAIL CORRECT RESPONSES … …

6. NCHUCS6 Scan Test (1)  A structural design-for-testability technique  Storage elements are not directly accessible  Scan test provides an easy way for test access Apply test patterns to circuit under test (CUT) Read output responses from CUT

7. NCHUCS7 Scan Test (2)  Sequential circuit FFs are neither controllable nor observable Combinational Logic Primary Input Primary Output F

8. NCHUCS8 Scan Test (3)  Normal signal path: parallel load Combinational Logic Primary Input Primary Output F

9. NCHUCS9 Scan Test (4)  In scan mode: a shift register Combinational Logic Primary Input Primary Output F Scan in (SI) Scan out (SO)

10. NCHUCS10 Scan Test (5)  To enable scan test Each scan cell has two inputs  Normal input  Scan input All scan cells are connected into a shift register (scan chain)  Turn a sequential test into a combinational one Apply test patterns directly Observe test results directly

11. NCHUCS11 Scan Chain  Normally constructed when placement and routing are done  The order does not matter  Find out the shortest scan chain order Traveling salesman problem (TSP) Asymmetric TSP (ATSP)  SI and SO of a scan cell are not at the same location NP-complete

12. NCHUCS12 Outline  Overview ■ Scan chain order: does it matter?  Cluster-based reordering for low- power BIST  Experimental results  Future work

13. NCHUCS13 Scan Test for Stuck-at Faults  Order does not matter As long as we can scan in test patterns and scan out test responses 1 01 0 CUT 1 01 0 1 01 0 1010 1100

14. NCHUCS14 Minimum Wirelength Routing  Use a TSP/ATSP solver Slow  Wirelength can be 10x with random order

15. NCHUCS15 Low-Power Testing  A great concern in recent years  Need to reduce signal transitions The source of dynamic power in CMOS Usually the dominant factor  Reorder scan chain to reduce switching activity 1 01 0 1010 1 01 0 1100 3 transitions 1 transition only

16. NCHUCS16 Delay Testing (1)  Require two-pattern tests First pattern: initialization Second pattern: launch transition  Delay test with simple scan chain Broadside  The output response of the 1st pattern are captured in the scan chain and become the 2nd pattern Skewed load  The 2nd pattern is the result of 1-bit shift of the 1st pattern

17. NCHUCS17 Delay Test (2)  Broadside test Eg. Apply v1=(1010), v2=(0100) Combinational Logic Primary Input Primary Output F 10101010 01000100 01000100

18. NCHUCS18 Delay Test (3)  Skewed load Not all test pairs possible  2 n 2 n possible 2-pattern combinations  Only 22 n possible with single scan chain Reorder scan chain to achieve higher fault coverage 1 01 0 1010 1 01 0 1100 0110 NOT POSSIBLE!! 0 110

19. NCHUCS19 Hold Time Violation  Not enough propagation delay between adjacent flip-flops in a sequential circuit Double latching  Possible solution Reorder scan cells to introduce extra delay

20. NCHUCS20 Outline  Overview  Scan chain order: does it matter? ■ Cluster-based reordering for lower-power BIST  Experimental results  Future work

21. NCHUCS21 Overview  Goal: Reduce BIST power  Approach Include a smoother to reduce switching activity in test pattern generator (TPG) Use scan chain reordering to recover lost fault coverage  Simple reordering algorithm  Wirelength should not increase too much

22. NCHUCS22 Overall Architecture Internal scan chain CUT ORA PRPGSmoother TPG Internal scan chain 1 Internal scan chain 2 Internal scan chain k........ ORAORA PRPGPRPG Smoother PhaseshifterPhaseshifter........ Single scan chain multiple scan chain

23. NCHUCS23 Smoother 0/1 1/0 0/0 1/0 0/0 1/0...... S n/2–1 S0S0 0/1 1/1 0/1 S n–1 S n/2...... 1/1 0/0 1/0 0/0 1/0 S1S1 0/1 1/1 S3S3 0/1 S0S0 S2S2 1/0 0/0 1/0 S1S1 S0S0 0/0 1/0 S3S3 S2S2 0/0 1/0 0/1 1/1 S5S5 S4S4 0/1 1/1 S7S7 S6S6 0/1 1/1 n-state smoother 4-state (2bit) smoother 8-state (3bit) smoother

24. NCHUCS24 A Simple Implementation of the n-state smother C Divide-by-n/2 Up-Down Counter T u d  q q  C0C0 in

25. NCHUCS25 Estimation of Power Reduction  Probability of signal transition of an n-state smoother Compute from Markov chain model  Estimation of dynamic power 2-bit (4-state ) smoother: 1/3 3-bit (8-state) smoother: 1/10

26. NCHUCS26 Fault Coverage 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 2-bit smoother3-bit smoother 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 1 0 0 PRPG  Smoothed patterns are less random May create repeated patterns and reduce fault coverage Required test cube: xxxxx01xxxxxxxx NO MATCH! Reorder scan chain: xxxxx0x1xxxxxxx MATCH 2-bit smoother

27. NCHUCS27 Cluster-Based Scan Chain Reorder  Layout surface divided into clusters  Reorder limited in single cluster  Snake-like global routing Single scan chain Multiple scan chains

28. NCHUCS28 Example  Routing s15850 611 scan cells 1 cluster 256 clustersSilicon Ensemble

29. NCHUCS29 Optimal Cluster Size  Is there an optimal cluster size?  Observation Large clusters--long vertical connection Small clusters--more horizontal crossings  How to find optimal cluster size Find an expression of total wirelength Take its derivative with respect to cluster size c

30. NCHUCS30 Estimate Wirelength in a Cluster (1)  Two types of order Random order Sorted according to x-cooridnate sc 1 sc 2 sc 4 sc 3 sc 5 CL 1 CL 2 sc 1 sc 2 sc 3 CL 1

31. NCHUCS31 Estimate Wirelength in a Cluster (2)  How to estimate the distance between two cells Manhattan distance Horizontal and vertical distances are independent Assuming cells are randomly distributed w (0, 0) h sc 1 (X 1, Y 1 ) sc 2 (X 2, Y 2 )

32. NCHUCS32 Estimate Wirelength in a Cluster (3)  Expected vertical distance between two cells  Expected horizontal distance between two cells Random order: w/3 Sorted order  Summation of all horizontal distances: w

33. NCHUCS33 Estimate Wirelength in a Cluster (4)  Random order N: # cells, c 2 : #clusters  Sorted order

34. NCHUCS34 Optimal Number of Clusters (1)  Random order Assuming H  W, N/c 2  1  Sorted order Assuming H  W, N/c 2  3

35. NCHUCS35 Optimal Number of Clusters (2)  Reordering algorithm Larger clusters give better results Almost no reordering when N/c 2  1 Choose sorted order if no special order is preferred  Optimal cluster size 2  N/c 2  3

36. NCHUCS36 Outline  Overview  Scan chain order: does it matter?  Cluster-based reordering for low- power BIST ■ Experimental results  Future work

37. NCHUCS37 Experimental Results — Wire Length (1)  2-bit smoother

38. NCHUCS38 Experimental Results — Wire Length (2)  3-bit smoother

39. NCHUCS39 Experimental Results — Fault Coverage (1)  2-bit smoother

40. NCHUCS40 Experimental Results — Fault Coverage (2)  3-bit smoother

41. NCHUCS41 Optimal Number of Cells per Cluster CircuitWL (mm) -- SE #cluster#cells/cluster2-bit smoother3-bit smoother GSWL (mm)Red (%)GSWL (mm)Red (%) S6412.71361.5022.83-4.2432.84-4.58 S7132.67361.5042.90-7.93102.90-7.93 S9533.30162.8133.68-10.3393.69-10.57 S11964.74162.0025.08-6.6975.09-6.88 S14235.70362.5316.04-5.5336.04-5.63 S537814.571002.14415.78-7.67415.77-7.61 S923422.681002.47123.21-2.28823.75-4.51 S1320745.222562.73344.741.06645.49-0.59 S1585053.402562.391051.972.68250.984.53 S38417136.945762.891123.39.966125.728.19 S38584187.895762.5410177.825.367178.145.19 SE: Silicon Ensemble

42. NCHUCS42 Test Efficienct CircuitTL Test Efficiency (%) Markov Source BIST LFSR2-bit smoother3-bit smoother SEOptimal ClusterSEOptimal Cluster S92347284898.5295.0293.4695.4783.3992.00 S132074067797.8898.9092.7397.8483.6487.72 S158503776798.3196.4193.4797.6990.6292.79 S384178198495.4297.2094.7995.9693.594.47 S385848205598.3699.7695.2999.2390.3595.82 Average-97.7097.4693.9597.2488.392.56

43. NCHUCS43 Comparison of Average Power Circuit#scan cells TLFC (%) LFSR 2-bit smoother*3-bit smoother*LT-RTPG  (k=3) FC (%) SE FC (%) Opt. cluster AP Red (%) FC (%) SE FC (%) Opt. cluster AP Red (%) FC (%)AP Red (%) S64154409697.4294.1995.9157.4187.3190.7585.6589.6436.9 S71354409691.9487.9989.8858.1583.70 86.3693.3437.8 S95345819298.9986.4197.9755.4754.2680.1784.9585.6158.7 S119632409695.4982.6392.7156.5859.4078.7285.4095.8730.2 S142391409697.8995.4098.5957.2588.7596.2985.0997.0849.7 S53782146553698.9697.9198.5658.5190.2695.5084.7597.0844.0 S923424713107289.6787.9191.4059.3777.4986.7885.5391.6355.7 S132077004067797.4291.2596.3762.6782.1786.2487.39-- S158506113776793.0690.1294.4358.2187.2789.4484.96-- S3841716648198496.6794.2695.4260.7392.9793.9384.93-- S3858414648205595.7091.0595.0060.8786.1491.5884.81-- Average-95.7590.8395.1158.6680.8888.4685.4492.8944.71 *Full scan;  : only state vectors are scanned

44. NCHUCS44 Peak Power  Capture-cycle power is not reduced  Still provide some improvement Circuit PP Red (%) 2-bit smoother3-bit smoother S537813.3111.64 S923413.7516.68 S1320712.6519.96 S1585013.6020.23 S3841713.7819.24 S3858413.1218.01 Average13.3717.63

45. NCHUCS45 Outline  Overview  Scan chain order: does it matter?  Cluster-based reordering for low- power BIST  Experimental results ■ Future work

46. NCHUCS46 Conclusion  Scan chain reorder is very effect to deal with Test power Scan-based delay test Fault coverage in BIST  Need to consider Physical design infromation

47. NCHUCS47 Future Work  Fast reordering algorithm for delay test  Integrate reordering algorithm, considering Test power Delay test coverage Wire length Other issues

48. NCHUCS48 THE END Thank You!