1. Improving Placement under the Constant Delay Model Kolja Sulimma 1, Ingmar Neumann 1, Lukas Van Ginneken 2, Wolfgang Kunz 1 1 EE and IT Department University of Kaiserslautern 2 Magma Design Automation Cupertino, CA, USA contact: kolja@sulimma.de

2. 2 Overview Conventional Delay Models detailed vs. abstract delay models timing driven placement and the critical path problem Constant Delay Model introduction placement under the constant delay model fast and exact area computation Experimental Results

3. 3 Delay of a CMOS Gate non-linear depends on many variables load capacitance input slew rate temperature supply voltage interconnect resistance crosstalk inductance? detailed tabular models can be used for timing analysis to irregular to guide the synthesis process load capacitance gate delay

4. 4 Unit Delay Model assumes all gates have the same delay independant of load, etc. performes astonishingly well not accurate enough in the deep sub micron age load capacitance unit delay model gate delay

5. 5 Linear Delay Model linear delay/load dependancy relatively accurate fit widely used for timing driven tool flows linear slew effects are commonly added to improve the model load capacitance linear delay model gate delay

6. 6 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires t critical

7. 7 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires t critical

8. 8 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires t critical

9. 9 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires t critical

10. 10 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires t critical

11. 11 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires delay of the gate and predecessors changes trivially t critical  

12. 12 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires delay of the gate and predecessors changes trivially t critical  

13. 13 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires delay of the gate and predecessors changes trivially t critical  

14. 14 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires delay of the gate and predecessors changes trivially t critical  

15. 15 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires delay of the gate and predecessors changes trivially but what about the critical path? ? t critical  

16. 16 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires delay of the gate and predecessors changes trivially but what about the critical path? ? t critical  

17. 17 Placement with Linear Delay Model arrange gates of fixed area to minimize the circuit delay moving a gate modifies the length (and capacitance) of adjacent wires delay of the gate and predecessors changes trivially but what about the critical path? ? t critical  

18. 18 ? t critical Placement with Linear Delay Model linear time needed to update circuit delay after cell move prohibitively slow common workarounds: optimisation of secondary criteria (e.g. wire length) heuristical net weights based on „ criticality “ of the net weights become stale after multiple moves increasingly inaccurate information about circuit delay t critical

19. 19 Constant Delay Model the models presented so far modeled the delay of a given gate implementation of constant size Constant Delay Model models the gate size required to meet a given constant gate delay requires a cell library that provides many cell sizes for each logic function it implements, or a cell that allows to size cells continously

20. 20 Constant Delay Model the delay of a gate is assumed to be constant load capacitance modeled delay

21. 21 Constant Delay Model the delay of a gate is assumed to be constant for any load capacitance a certain gate size is required to achieve this delay load capacitance modeled area modeled delay

22. 22 Constant Delay Model the delay of a gate is assumed to be constant for any load capacitance a certain gate size is required to achieve this delay this gate size ideally depends linearly on the load capacitance load capacitance modeled area modeled delay CC AA

23. 23 Constant Delay Model the delay of a gate is assumed to be constant for any load capacitance a certain gate size is required to achieve this delay this gate size ideally depends linearly on the load capacitance if there is only a fixed set of gate sizes the actual area will deviate from the model load capacitance actual area modeled area modeled delay

24. 24 Constant Delay Model the delay of a gate is assumed to be constant for any load capacitance a certain gate size is required to achieve this delay this gate size ideally depends linearly on the load capacitance if there is only a fixed set of gate sizes the actual area will deviate from the model this causes the actual delay to deviate from the model load capacitance actual area modeled area actual delay modeled delay

25. 25 Constant Delay Model the delay of a gate is assumed to be constant for any load capacitance a certain gate size is required to achieve this delay this gate size ideally depends linearly on the load capacitance if there is only a fixed set of gate sizes the actual area will deviate from the model this causes the actual delay to deviate from the model fortunately, this effect is alleviated by load effects on the preceeding gates actual area modeled area actual delay including preceeding stage modeled delay

26. 26 Constant Delay Model: Placement find a placement minimising the circuit area for a given circuit delay note: ideally all cells remain critical during the placement process avoids critical path problem we propose a new approach based on net weights that measure exactly how a local change of the wire capacitance effects the overall circuit area can be computed efficiently in advance remain valid throughout the placement process

27. 27 i Constant Delay Model: Circuit Area gate area A i increases linearly with the load capacitance C i seen at gate i. i

28. 28 Constant Delay Model: Circuit Area the input capacitance C ij of any input j of gate i increases linearly with the load capacitance i j

29. 29 Constant Delay Model: Circuit Area this in turn increases the area A j of the predecessor gate linearly i j j

30. 30 Constant Delay Model: Circuit Area this in turn increases the area A j of the predecessor gate linearly as a result a capacitance change at a node causes a linear increase in area on all predecessor gates i j j

31. 31 i j Constant Delay Model: Circuit Area the total circuit area A is the sum of all gate areas A i changes linearly with C i i j

32. 32 Constant Delay Model: Circuit Area the total circuit area A is the sum of all gate areas A i changes linearly with C i global area sensitivity i j i j

33. 33 Area Sensitivities and Placement area of the circuit and the individual gates may change during the placement process, but the area sensitivity never does. area sensitivities allow to accurately compute the effect of a cell move on circuit area for a gate move placer can directly optimise circuit area without heuristic weights we only know the size of the overall circuit but not the sizes of the individual gates or partitions. This can introduce small inaccuracies in the wire length calculation.

34. 34 Area Sensitivities area sensitivities for all gates can be computed in advance: linear sweep for combinational circuits inversion of a sparse matrix for sequential circuits

35. 35 Area Sensitivities area sensitivities for all gates can be computed in advance: linear sweep for combinational circuits inversion of a sparse matrix for sequential circuits details are shown in the paper

36. 36 Experiments existing timing driven toolflow was modified to support the constant delay model original flow used for comparison both flows use FM-based recursive bipartitioning half perimeter wire length estimate technology mapping for hypothetical cell generator for arbitrary series- parallel CMOS cells designer choses target delay from area/delay tradeoff curve

37. 37

38. 38 Experimental Results

39. 39 Conclusion we exploit properties of the constant delay model to simplify and improve the placement process the exact area costs of a cell move can be calculated based on area sensitivities 15% area improvement compared to conventional approach computationally efficient