1. January 28th, 2010Clermont Ferrand, Paul Scherrer Institut DRS Chip Developments Stefan Ritt

2. January 28th, 2010Clermont Ferrand, Agenda DRS4 chip has been developed at PSI and has been shown at this Workshop in Lyon 2008 No new chip development since 2008, but – deployment of 3000 channels in the MEG experiment – many chips and boards shipped worldwide Experiences in designing large systems Some new ideas about next generation DRS4 Chip DRS4 Chip Evaluation Board

3. Stefan RittJanuary 28th, 2010Clermont Ferrand, DRS4 Fabricated in 0.25  m 1P5M MMC process (UMC), 5 x 5 mm2, radiation hard 8+1 ch. each 1024 bins, 4 ch. 2048, …, 1 ch. 8192 Differential inputs/ outputs Sampling speed 500 MHz … 6 GHz On-chip PLL stabilization Readout speed 30 MHz, multiplexed or in parallel

4. Stefan RittJanuary 28th, 2010Clermont Ferrand, DRS4 @ MEG 4 x DRS4 LMK03000 32 channels 3000 Channels

5. Stefan RittJanuary 28th, 2010Clermont Ferrand, DRS4 around the world

6. Stefan RittJanuary 28th, 2010Clermont Ferrand, Worldwide Community 750 chips and 50 evaluation boards shipped worldwide Community forming sharing ideas helping each other more elaborate chip characterization helps to reduce chip prices motivate other groups to develop their own SCA Pushing the field of SCA technology forward 750 chips and 50 evaluation boards shipped worldwide Community forming sharing ideas helping each other more elaborate chip characterization helps to reduce chip prices motivate other groups to develop their own SCA Pushing the field of SCA technology forward

7. Stefan RittJanuary 28th, 2010Clermont Ferrand, The problem of big systems  t=1 ps how to synchronize? Machine RF

8. Stefan RittJanuary 28th, 2010Clermont Ferrand, Jitter Measurement 1 Use LeCroy WavePro 7300A (3 GHz, 20 GSPS) with analysis statistics:

9. Stefan RittJanuary 28th, 2010Clermont Ferrand, Problems Low Gain: Scope noise (6-7 bit) leads to timing jitter  overestimation High Gain: Not enough sample points in window  underestimation Single ended probe:  20 ps Differential probe:  2 ps Single ended probe:  20 ps Differential probe:  2 ps

10. Stefan RittJanuary 28th, 2010Clermont Ferrand, Jitter Analysis with SA carrier frequency (e.g. 20 MHz) 85 k$

11. Stefan RittJanuary 28th, 2010Clermont Ferrand, Quarz Jitter

12. Stefan RittJanuary 28th, 2010Clermont Ferrand, PLL Behavior Quartz through FPGA: Quartz through DCM: Improvement 9 ps  1.3 ps if FPGA clock was turned off! 9ps 23ps

13. Stefan RittJanuary 28th, 2010Clermont Ferrand, First Results Measured Jitter WavePro 7300A Agilent E5052A 1 kHz – 20 MHz Data Sheet 66 MHz Quartz Oscillator8 ps3.8 ps<1 ps 66 MHz Quartz through FPGA18 ps9 ps 66 MHz Quartz through DCM23 ps22 ps100 ps Quartz FPGA DCM

14. Stefan RittJanuary 28th, 2010Clermont Ferrand, Jitter with differential signals voltage noise band of signal timing jitter arising from voltage noise timing jitter is much smaller for faster rise-time Single EndedDifferential +-

15. Stefan RittJanuary 28th, 2010Clermont Ferrand, Differential Signals through FPGA Quartz FPGA DCM Differential clocks won’t help! VDD/2 t’t VDD noise

16. Stefan RittJanuary 28th, 2010Clermont Ferrand, DRS4 @ MEG Temperature Stabilized Master Quartz LVDS fan-out 20 MHz 200 low jitter LVDS lines Is the jitter low enough or should we use a jitter cleaner?

17. Stefan RittJanuary 28th, 2010Clermont Ferrand, LMK03000 20 MHz 1.2 GHz 1.56 MHz 240 MHz LMK03000 Clock Conditioner (National Semiconductor) Jitter: 400 fs

18. Stefan RittJanuary 28th, 2010Clermont Ferrand, Measurement with test board FPGA output

19. Stefan RittJanuary 28th, 2010Clermont Ferrand, Phase Jitter after cleaner National Semiconductor Application Note AN-1734

20. Stefan RittJanuary 28th, 2010Clermont Ferrand, Timing Big Systems II Channel 0 Inverter Chain Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 PLL LMK03000 Experiment wide global clock SCA Chip Global clock locks all DRS4 PLLs to same frequency and phase Residual PLL jitter: 25 ps Even better timing can be obtained by direct clock sampling: 2 ps MEG Experiment: Single LVDS clock distributed over 9 VME crates

21. Stefan RittJanuary 28th, 2010Clermont Ferrand, Global Timing 1 120 LMK03000 MEG Clock 20 MHz FPGA DRS4 REFCLK PLL CH9 240 MHz 120 EN 120

22. Stefan RittJanuary 28th, 2010Clermont Ferrand, Global Timing 2 120 LMK03000 MEG Clock 20 MHz FPGA DRS4 REFCLK PLL CH9 240 MHz 120 EN 120 Driven by FPGA missing MEG clock Driven by FPGA missing MEG clock

23. Stefan RittJanuary 28th, 2010Clermont Ferrand, Global Timing 3 120 LMK03000 MEG Clock 20 MHz FPGA DRS4 REFCLK PLL CH9 240 MHz 120 EN 120 Driven by MEG clock

24. Stefan RittJanuary 28th, 2010Clermont Ferrand, Synchronization of clock chips 1.2 GHz 1.56 MHz Chip 1 1.56 MHz Chip 2 n * 0.83 ns SYNC & 20 MHz SYNC has to arrive on all board within 50 ns  trigger bus 20 MHz MEG clock has to arrive on all boards within 0.83 ns SYNC has to arrive on all board within 50 ns  trigger bus 20 MHz MEG clock has to arrive on all boards within 0.83 ns 20 MHz 50 ns

25. Stefan RittJanuary 28th, 2010Clermont Ferrand, What we learn from LMK03000 Differential inverter chain  VDD noise cancels Use only small VCO range LMK03000: 1185-1296 MHz Use partly internal and external loop filter Use separate VDD and GND for PLL use LDO on chip Consider for next generation SCA design

26. Stefan RittJanuary 28th, 2010Clermont Ferrand, Away from crate-based systems 1 k$/slot fiber optics G. Varner: BLAB2 readout system for f-DIRC G. Varner: BLAB2 readout system for f-DIRC WaveDREAM Board (PSI) WaveDREAM Board (PSI) GBit Ethernet

27. Stefan RittJanuary 28th, 2010Clermont Ferrand, Next Generation SCA Low parasitic input capacitance  High bandwidth Large area  low resistance bus, low resistance analog switches  high bandwidth Short sampling depth Digitize long waveforms Accommodate long trigger delay Faster sampling speed for a given trigger latency Deep sampling depth How to combine best of both worlds? How to combine best of both worlds?

28. Stefan RittJanuary 28th, 2010Clermont Ferrand, Cascaded Switched Capacitor Arrays shift register input fast sampling stage secondary sampling stage................................. 32 fast sampling cells (10 GSPS/130nm CMOS) 100 ps sample time, 3.1 ns hold time Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) Shift register gets clocked by inverter chain from fast sampling stage 32 fast sampling cells (10 GSPS/130nm CMOS) 100 ps sample time, 3.1 ns hold time Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) Shift register gets clocked by inverter chain from fast sampling stage

29. Stefan RittJanuary 28th, 2010Clermont Ferrand, How is timing resolution affected? voltage noise  u timing uncertainty  t signal height U rise time t r number of samples on slope

30. Stefan RittJanuary 28th, 2010Clermont Ferrand, How is timing resolution affected? U uu fsfs f 3db tt 100 mV1 mV2 GSPS300 MHz10 ps 1 V1 mV2 GSPS300 MHz1 ps 100 mV1 mV10 GSPS3 GHz1 ps today: optimized SNR: next generation: includes detector noise in the frequency region of the rise time and aperture jitter

31. Stefan RittJanuary 28th, 2010Clermont Ferrand, Conclusions SCA community growing! Building big systems with O(ps) accuracy is tough but possible New generation of SCA chips on the horizon