Presentation is loading. Please wait.

Presentation is loading. Please wait.

Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Top-Down and Bottom-Up Approaches to Stable Clock.

Published bySerenity Bettes Modified over 9 years ago

Similar presentations

Presentation on theme: "Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Top-Down and Bottom-Up Approaches to Stable Clock."— Presentation transcript:

1 Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Top-Down and Bottom-Up Approaches to Stable Clock Synthesis Solid State Electronics Laboratory Center for Wireless Integrated Microsystems (WIMS) Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, MI USA 48109-2122 International Conference on Electronic Circuits and Systems, Sharjah, U.A.E., 2003

2 2 NSF ERC for Wireless Integrated MicroSystems (WIMS) Lecture Overview Overview of Clock Synthesis Effects of Frequency Translation on Frequency Stability Top-Down and Bottom-Up Synthesis Application Design and Simulation Results Conclusions and Future Work OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

3 3 NSF ERC for Wireless Integrated MicroSystems (WIMS) Clock Synthesis The clock is arguably the most significant signal in any synchronous system Harmonic quartz XTAL reference + PLL is the ubiquitous approach –High accuracy and stability –Broad range of output frequencies Drawbacks –Discrete components required (not monolithic) –PLL power and area –Systemic short-term stability degradation (to be presented) Challenges in developing an alternative (possibly monolithic) approach –Accuracy and stability –Monolithic reference (typically low- Q ) OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

4 4 NSF ERC for Wireless Integrated MicroSystems (WIMS) Short-Term Frequency Stability Metrics Phase Noise: Power relative to fundamental at some offset f m f fofo P fmfm Period Jitter:  of the position of the next edge relative to the ideal Ideal Period Period Jitter tktk t k+1 OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

5 5 NSF ERC for Wireless Integrated MicroSystems (WIMS) Frequency Multiplication and Division Phase and frequency are related by a linear operator: Frequency mult./div. results in phase noise mult./div.: Using narrowband FM approximation: Linear freq. translation results in quadratic change in noise power Overview Freq. Trans. SynthesisApplicationDesign & Sim.ResultsConclusions

6 6 NSF ERC for Wireless Integrated MicroSystems (WIMS) Converting Phase Noise to Period Jitter Typically  f o 2 c called corner or line width: select f m above the corner and below f o Lorentzian implies absence of flicker noise (slope must be 20dB/dec) The SSB phase noise PSD can be represented by a Lorentzian function: fmfm 20dB/dec Which can be approximated for: Using the above: OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

7 7 NSF ERC for Wireless Integrated MicroSystems (WIMS) Frequency Translation and Jitter Using phase noise conversion expression, determine jitter: Considering fractional, or ppm, jitter: Frequency translation also enhances and degrades jitter OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

8 8 NSF ERC for Wireless Integrated MicroSystems (WIMS) Relationship with Quality-Factor Leeson model: Q -factor quadratically related to phase noise Q -factor is one of the most significant metrics indicating stability Typical quartz XTAL Q on the order of 10,000 Frequency translation also quadratically related to phase noise Consider effective Q -factor modification due to freq. translation If N div N mult > Q mult /Q div then divided signal more stable Assumption: oscillator power and noise factor are the same N mult for XTAL+ PLL up to 4096: high- Q, but large degradation Leeson Phase Noise Model OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

9 9 NSF ERC for Wireless Integrated MicroSystems (WIMS) Frequency Translation Summary Variable/Metric Reference Oscillator Frequency Multiplication Frequency Division Output Frequency (Hz) f ref Nf ref f ref /N SSB Phase Noise PSD (dBc/Hz) Period Jitter (s) J Relative Period Jitter (ppm) J ppm OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

10 10 NSF ERC for Wireless Integrated MicroSystems (WIMS) A Bottom-Up Approach ÷N Nf ref LPF v ctrl f ref CPPFD Quartz XTAL reference oscillator + PLL The signal that actually drives the processor is a frequency multiplied (and degraded) image of the reference OverviewFreq. Trans. Synthesis ApplicationDesign & Sim.ResultsConclusions

11 11 NSF ERC for Wireless Integrated MicroSystems (WIMS) A Top-Down Approach ÷N f ref f ref N A harmonic LC (and monolithic) RF reference The signal that actually drives the processor is a frequency divided (and enhanced) image of the reference LC reference also provides good accuracy as compared to ring or relaxation approach OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

12 12 NSF ERC for Wireless Integrated MicroSystems (WIMS) Application Test Bench Intel SA-1110 –3.6864MHz XTAL reference + PLL –~200MHz max output frequency Bottom-up Approach –3.125MHz XTAL, Q = 10,000 –Output = 200MHz, N = 64 Top-down Approach –3.2GHz reference, Q = 10 –Output = 200MHz, N = 16 All transistor design with TSMC 0.18 MM/RF OverviewFreq. Trans.Synthesis Application Design & Sim.ResultsConclusions

13 13 NSF ERC for Wireless Integrated MicroSystems (WIMS) Pierce Bottom-Up XTAL Reference OSC 30 1 50 1 389m4.79f 900 30p 7p 500k 3.125MHz XTAL reference Requires off-chip XTAL + 2 capacitors + 1 resistor XTAL lumped parameter model OverviewFreq. Trans.SynthesisApplication Design & Sim. ResultsConclusions

14 14 NSF ERC for Wireless Integrated MicroSystems (WIMS) Ring Bottom-Up VCO 4 0.18 2 0.18 4 0.18 2 0.18 4 0.18 2 0.18 bias from last stage 20-stage 200MHz current-starved ring VCO OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

15 15 NSF ERC for Wireless Integrated MicroSystems (WIMS) A Bottom-Up System LPFPFD ÷N f ref Nf ref v ctrl CP Remainder of PLL modeled with Verilog-A OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

16 16 NSF ERC for Wireless Integrated MicroSystems (WIMS) LC Top-Down Reference OSC 40 0.18 100 0.18 40 0.18 100 0.18 36 0.18 2nH bias 950fF 3.2GHz monolithic RF LC reference oscillator OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

17 17 NSF ERC for Wireless Integrated MicroSystems (WIMS) Top-Down System Implementation Entire system designed at the device level Each feedback flip-flop divides frequency by two OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions DFF Q Q D AMP + - 3.2GHz Q Q D Q Q D DFF Q D Q 200MHz

18 18 NSF ERC for Wireless Integrated MicroSystems (WIMS) Design and Simulation Bottom-up Approach –Phase noise for reference OSC and VCO simulated at device level –Device-level results modeled with Verilog-A –Entire PLL modeled with phase domain approach using Verilog-A Top-down Approach –Entire system simulated at the device level OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

19 19 NSF ERC for Wireless Integrated MicroSystems (WIMS) Bottom-Up Phase Noise Performance OverviewFreq. Trans.SynthesisApplicationDesign & Sim. Results Conclusions

20 20 NSF ERC for Wireless Integrated MicroSystems (WIMS) Bounding PLL Phase Noise OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

21 21 NSF ERC for Wireless Integrated MicroSystems (WIMS) Top-Down Phase Noise Performance OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

22 22 NSF ERC for Wireless Integrated MicroSystems (WIMS) Performance Comparison Performance MetricBottom-Up SynthesisTop-Down Synthesis Application Frequency, f o (MHz) 200 Reference Oscillator Frequency, f ref (MHz) 3.1253,200 Multiplication/Division Factor, N 6416 Reference Oscillator Quality Factor, Q 10,00010 Reference Oscillator Phase Noise Density, ( N o / P o ) f m (dBc/Hz) -140.8dBc/Hz @ 10kHz-83dBc/Hz @ 10kHz Calculated Period Jitter at Reference from ( N o / P o ) f m @ 10kHz offset, J (fs) 2335.5 Calculated Relative Period Jitter at Reference, J ppm (ppm) 0.7318 Synthesizer Output Phase Noise Density, ( N o / P o ) f m (dBc/Hz) -104.6dBc/Hz @ 10kHz-106.8 @ 10kHz Calculated Period Jitter at Output from ( N o / P o ) f m @ 10kHz offset, J (fs) 2923 Calculated Relative Period Jitter at Output J ppm (ppm) 5.94.6 Phase Noise Density Accumulation/Reduction Factor, (dB) 36.2-23.8 Period Jitter Accumulation/Reduction Factor 0.124.2 Relative Period Jitter Accumulation/Reduction Factor 8.00.23 OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

23 23 NSF ERC for Wireless Integrated MicroSystems (WIMS) Conclusions and Future Work Frequency multiplication degrades short term stability and effectively reduces reference oscillator Q Frequency division enhances short-term stability and effectively increases reference oscillator Q Bottom-up approach requires reference XTAL OSC + PLL while top- down approach requires only reference OSC + divider For a common application, top-down approach provides comparable frequency stability to bottom-up approach, while being substantially simpler to implement Top-down approach facilitates monolithic integration Such a clock synthesis system has been developed and will be reported in the near future More sophisticated top-down architectures will be explored OverviewFreq. Trans.SynthesisApplicationDesign & Sim.Results Conclusions

24 24 NSF ERC for Wireless Integrated MicroSystems (WIMS) Conclusions and Future Work Questions? OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

Download ppt "Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Top-Down and Bottom-Up Approaches to Stable Clock."

Similar presentations

A Stabilization Technique for Phase-Locked Frequency Synthesizers Tai-Cheng Lee and Behzad Razavi IEEE Journal of Solid-State Circuits, Vol. 38, June 2003.

A Stabilization Technique for Phase-Locked Frequency Synthesizers Tai-Cheng Lee and Behzad Razavi IEEE Journal of Solid-State Circuits, Vol. 38, June 2003.
HARP-B Local Oscillator

HARP-B Local Oscillator
Mobius Microsystems Microsystems Mbius Slide 1 of 21 A 9.2mW 528/66/50MHz Monolithic Clock Synthesizer for Mobile µP Platforms Custom Integrated Circuits.

Mobius Microsystems Microsystems Mbius Slide 1 of 21 A 9.2mW 528/66/50MHz Monolithic Clock Synthesizer for Mobile µP Platforms Custom Integrated Circuits.
Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Study and Simulation of CMOS LC Oscillator Phase Noise.

Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Study and Simulation of CMOS LC Oscillator Phase Noise.
A Resonant Clock Generator for Single-Phase Adiabatic Systems Conrad H. Ziesler Marios C. Papaefthymiou University of Michigan, Ann Arbor, MI Suhwan Kim.

A Resonant Clock Generator for Single-Phase Adiabatic Systems Conrad H. Ziesler Marios C. Papaefthymiou University of Michigan, Ann Arbor, MI Suhwan Kim.
S-72.245 Transmission Methods in Telecommunication Systems (4 cr) Carrier Wave Modulation Systems.

S Transmission Methods in Telecommunication Systems (4 cr) Carrier Wave Modulation Systems.
Lecture 17: Analog to Digital Converters Lecturers: Professor John Devlin Mr Robert Ross.

Lecture 17: Analog to Digital Converters Lecturers: Professor John Devlin Mr Robert Ross.
Electronics Principles & Applications Sixth Edition Chapter 13 Integrated Circuits (student version) ©2003 Glencoe/McGraw-Hill Charles A. Schuler.

Electronics Principles & Applications Sixth Edition Chapter 13 Integrated Circuits (student version) ©2003 Glencoe/McGraw-Hill Charles A. Schuler.
Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, and Richard B. Brown.

Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, and Richard B. Brown.
M. McCorquodale, A.-C. Wong, K. Nagarajan, H. Kulah, C. T.-C. Nguyen University of Michigan An Integrated MEMS-BiCMOS SINCGARS Transceiver Design Automation.

M. McCorquodale, A.-C. Wong, K. Nagarajan, H. Kulah, C. T.-C. Nguyen University of Michigan An Integrated MEMS-BiCMOS SINCGARS Transceiver Design Automation.
Ultra Low Power PLL Implementations Sudhanshu Khanna ECE7332 2011.

Ultra Low Power PLL Implementations Sudhanshu Khanna ECE
A CMOS Front-end Amplifier Dedicated to Monitor Very Low Amplitude Signals from Implantable Sensors ECEN 5007 Mixed Signal Circuit Design Sandra Johnson.

A CMOS Front-end Amplifier Dedicated to Monitor Very Low Amplitude Signals from Implantable Sensors ECEN 5007 Mixed Signal Circuit Design Sandra Johnson.
Ayman Khattab Mohamed Saleh Mostafa El-Khouly Tarek El-Rifai

Ayman Khattab Mohamed Saleh Mostafa El-Khouly Tarek El-Rifai
Chapter Two: Radio-Frequency Circuits. Introduction There is a need to modulate a signal using an information signal This signal is referred to as a baseband.

Chapter Two: Radio-Frequency Circuits. Introduction There is a need to modulate a signal using an information signal This signal is referred to as a baseband.
Oscillator Circuits. Outline Oscillators – Inverter-Based Oscillator – Introduction of Phase Noise Simulation – LC-Tank Based Oscillator Laplace Analysis.

Oscillator Circuits. Outline Oscillators – Inverter-Based Oscillator – Introduction of Phase Noise Simulation – LC-Tank Based Oscillator Laplace Analysis.
GUIDED BY: Prof. DEBASIS BEHERA

GUIDED BY: Prof. DEBASIS BEHERA
Lecture 22: PLLs and DLLs. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 22: PLLs and DLLs2 Outline  Clock System Architecture  Phase-Locked Loops  Delay-Locked.

Lecture 22: PLLs and DLLs. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 22: PLLs and DLLs2 Outline  Clock System Architecture  Phase-Locked Loops  Delay-Locked.
Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006.

Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006.
LLRF Phase Reference System The LCLS linac is broken down into 4 separate linac sections. The LCLS injector will reside in an off axis tunnel at the end.

LLRF Phase Reference System The LCLS linac is broken down into 4 separate linac sections. The LCLS injector will reside in an off axis tunnel at the end.
1 Phase-Locked Loop. 2 Phase-Locked Loop in RF Receiver BPF1BPF2LNA LO MixerBPF3IF Amp Demodulator Antenna RF front end PD Loop Filter 1/N Ref. VCO Phase-

1 Phase-Locked Loop. 2 Phase-Locked Loop in RF Receiver BPF1BPF2LNA LO MixerBPF3IF Amp Demodulator Antenna RF front end PD Loop Filter 1/N Ref. VCO Phase-

Similar presentations

Ads by Google