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Survey of Reconfigurable Logic Technologies

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1 Survey of Reconfigurable Logic Technologies
ECE 448 Lecture 17 Survey of Reconfigurable Logic Technologies ECE 448 – FPGA and ASIC Design with VHDL

2 Required reading S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 3.6 Programmable Logic Devices ECE 448 – FPGA and ASIC Design with VHDL

3 Main source Clive „Max” Maxfield, The Design Warrior’s Guide to FPGAs
Chapter 2 Fundamental Concepts Chapter 3 The Origin of FPGAs Chapter 4 Alternative FPGA Architectures ECE 448 – FPGA and ASIC Design with VHDL

4 Technology Timeline ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

5 Programmable Logic Devices
ECE 448 – FPGA and ASIC Design with VHDL

6 First Programmable Logic Devices
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

7 Programmable logic device as a black box
Logic gates and programmable switches Inputs (logic variables) Outputs (logic functions) ECE 448 – FPGA and ASIC Design with VHDL

8 General structure of a PLA (Programmable Logic Array)
x x x 1 2 n Input buffers & inverters x x x x 1 1 n n P 1 AND plane OR plane P k f f 1 m ECE 448 – FPGA and ASIC Design with VHDL

9 Gate-level diagram of a PLA
x x x 1 2 3 Programmable connections OR plane P 1 P 2 P 3 P 4 AND plane f 1 f 2 ECE 448 – FPGA and ASIC Design with VHDL

10 Customary schematic for a PLA
1 P 2 x 3 OR plane AND plane 4 ECE 448 – FPGA and ASIC Design with VHDL

11 Programmable Array Logic
f 1 P 2 x 3 AND plane 4 ECE 448 – FPGA and ASIC Design with VHDL

12 Macrocell at the output of PAL
1 To AND plane D Q Clock Select Enable Flip-flop ECE 448 – FPGA and ASIC Design with VHDL

13 A generic structure of CPLD (Complex Programmable Logic Device)
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

14 Structure of a CPLD Interconnection wires I/O block PAL-like block
ECE 448 – FPGA and ASIC Design with VHDL

15 A section of a CPLD ECE 448 – FPGA and ASIC Design with VHDL D Q
PAL-like block ECE 448 – FPGA and ASIC Design with VHDL

16 Connections between the programmable interconnect matrix and simple PAL-like blocks
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

17 Field Programmable Gate Arrays
ECE 448 – FPGA and ASIC Design with VHDL

18 The world of ASICs ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

19 Gap between PLDs and ASICs
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

20 General structure of an FPGA
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

21 Mux-Based Logic Block ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

22 LUT-Based Logic Block ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

23 Xilinx Multipurpose LUT
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

24 Simplified view of a Xilinx Logic Cell
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

25 Xilinx CLB Slice ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

26 Xilinx CLB ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

27 RAM Blocks and Multipliers in Xilinx FPGAs
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

28 Additional cores outside of the main fabric
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

29 Embedded Microprocessor Cores
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

30 A simple clock tree ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

31 Clock Manager ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

32 Jitter ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

33 Removing Jitter ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

34 Frequency Synthesis ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

35 Phase shifting Figure 4-20 ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Figure 4-20 ECE 448 – FPGA and ASIC Design with VHDL

36 Removing Clock Skew ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

37 General-Purpose IO Blocks
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

38 Using High-Speed Tranceivers to Communicate Between Devices
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

39 Programming Reconfigurable
Logic Devices ECE 448 – FPGA and ASIC Design with VHDL

40 A Fusible Link Technologies: Unprogrammed Device
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

41 A Fusible Link Technologies: Programmed Device
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

42 An Antifuse Technology: Unprogrammed Device
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

43 An Antifuse Technology: Programmed Device
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

44 Growing an Antifuse ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

45 EPROM Technology ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

46 An EPROM Transistor-Based Memory Cell
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

47 EEPROM Technology ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

48 Static RAM-based Technology
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

49 Summary of Programming Technologies
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

50 ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

51 Programming a PLD ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

52 A PLD Programming Unit (courtesy of Data IO Corp).
ECE 448 – FPGA and ASIC Design with VHDL

53 Configuration of SRAM based FPGAs
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

54 FPGA Configuration Modes
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

55 Serial Load with FPGA as a Master
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

56 Daisy-Chaining FPGAs ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

57 Parallel Load with FPGA as a Master (off-the-shelf memory)
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

58 Parallel Load with FPGA as a Master (special-purpose memory)
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

59 Parallel Load with FPGA as a Slave
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

60 Using the JTEG Port JTEG = Joint Test Action Group, IEEE 1149.1
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

61 Internal Processor Boundary Scan Chain
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( ECE 448 – FPGA and ASIC Design with VHDL

62 Reconfiguration Interfaces in Xilinx FPGAs
Internal Port ICAP (Virtex-II) JTAG SelectMap (8 bits Parallel) ECE 448 – FPGA and ASIC Design with VHDL

63 Configuration times of selected FPGA devices
ECE 448 – FPGA and ASIC Design with VHDL

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