1. Parallel I/O

2. Introduction oThis section focuses on performing parallel input and output operations on the 68HC11 o3 operation types oSimple, blind data transfers oStrobed transfers oTransfers with handshaking oLook at examples of each transfer operation Contd …

3. SEGMENT code Introduction oReading: oText, Chap 9: oRead: 9.1, 9.4-9.8.1 oScan: 9.2, 9.3 oE9: Section 6

4. 7 Recall the block diagram of the 68HC11

5. Simple I/O operations oThese I/O operations take place under the direction of the processor oOperations are performed without regard to the status of the I/O port the port is always assumed to be "ready" Contd …

6. Simple I/O operations oSince the current status of the port is not known, it is possible to oRead the same value in more than once on input operations oOverwrite the current value in an output port that is waiting to be transferred o"Good" examples of use: oInput initialization values from a port port is in known state as a result of system reset oI/O when overwrites or multiple reads don't matter writing to the hex display’s port in the labs, for example

7. Simple I/O operations Simple I/O example -- keypad interface Consider the simple 12- key keypad shown below

8. Simple I/O operations Simple I/O example -- keypad interface Consider the simple 12- key keypad shown below

9. Simple I/O operations oHigh-level procedure to detect key closures oDrive Row 1 input low oRead Columns -- any =0? oRepeat this process for all remaining rows until “see” a column=0 oIf no column=0, then no key has been depressed

10. Simple I/O operations oKnowing which row and column were low permits you to calculate the key number that was pressed oCan use a simple equation (similar to the approach of Listing 9.5) oKey# = col# + (3*row#) -3 oAssumes row and col numbers start with 1 oListing 9.5 is for 2-of-7 keyboard! oOr use a lookup table (similar to the approach in Listing 9.10) o– Assumes row and col use same port (port C)

11. Simple I/O operations oKey debounce oNeed to avoid the multiple make/break closures associated with key bounce o“Simple” approach is ID the key closed and then wait for a period of time to see if the key is still closed (therefore not bouncing) oThen and only then, return the key value oThe waiting period will vary from switch to switch -- 10s to 100s of ms

12. Simple I/O operations oHow will the system react if you hold a key down for a long time? oShould an action (in response to a key closure) be repeated over and over despite there being only 1 switch closure “action” oShould the action take place only once and then wait for the key “break” before recognizing another closure? oConsider routines to recognize key makes and breaks

13. Strobed I/O oThis method of performing I/O operations uses a control line, the strobe, to notify the receiving unit of the availability of data at its (input) port oThe process: oDevice performing the write places data onto data bus (its output port) oStrobe signal is asserted (for 2 cycles in 68HC11) oStrobe signal causes data to be latched into input port of the receiving device Contd …

14. Strobed I/O oStrobe signal causes an I/O interrupt to occur or a flag to be set -- in either case the receiving device is signaled that new data has arrived oIt is up to the receiving device to read the new data at its input port in a "timely" fashion oProblem oIf a second data item arrives at the input port and is strobed in (latched) before the input device has read the first item, the first item will be overwritten and lost

15. Strobed I/O o68HC11 register support for strobed I/O oDDRC -- data direction register for port C oPORTCL -- port C input latch -- data is latched on STRA edge oPORTC -- input pins for port C -- not latched oPORTB -- latched output data port B – outputs data using STRB oPIOC -- parallel I/O control register oPORTD -- bits 6 and 7 are STRA and STRB Contd …

16. Strobed I/O

17. oStrobed input operations using port C oData is placed at the input pins of port C oSTRA is asserted by peripheral device, causing oData to be latched into PORTCL oSTAF flag to be asserted oInterrupt initiated, if interrupts are enabled oData is read into to processor from PORTCL oTo clear STAF, read PIOC first then PORTCL

18. Strobed I/O

19. oStrobed Output oPeripheral device is connected to Port B oWhen the MCU writes to Port B,... oData is placed on Port B pins oSTRB is asserted for 2 clock cycles oPeripheral device should use STRB to latch the data oSTRB can be configured as active-high or active-low

20. Handshaking I/O oIn this mode, the sending and receiving devices exchange positive sent/received signals to one another oInsures that each transmitted word is received before the next word is transmitted

21. Handshaking I/O oTransfers can occur in either the pulsed or the interlocked method oPulsed input operations oPeripheral pulses STRA to indicate that data is present oWhen 68HC11 reads the data (from PORTCL), it automatically generates an acknowledgment strobe on STRB for 2 cycles oThis mode is selected by initializing the PLS bit (bit 2 of the PIOC) to 1

22. Handshaking I/O oTransfers can occur in either the pulsed or the interlocked method oInterlocked input operations oHere, STRB acts as a READY signal oAsserted = 68HC11 ready to receive data oNegated = 68HC11 is not ready -- do not send data now

23. Handshaking I/O

24. oOutput operations with handshaking oPort C is used for output handshake operations, along with STRB and STRA o– STRB is the output "data available" strobe o– STRA is the acknowledgment / input ready strobe line oPIOC bit 3, OIN, set to 1 for output operations oPulsed operations o68HC11 writes data to PORTCL and automatically asserts STRB for 2 cycles oPeripheral device reads data upon receipt of the STRB strobe oPeripheral asserts its READY line (68HC11's input STRA line) to signal receipt of data oPIOC bit 2, PLS set to 1 for pulsed mode

25. Handshaking I/O oOutput operations with handshaking oInterlocked mode oUpon writing data to PORTCL, STRB is asserted oSTRB negated only upon ACK

26. Handshaking I/O

27. oHandshaking example: Centronics parallel printer interface oThe "Centronics" definition of a printer port interface has become the standard parallel printer interface

28. Handshaking I/O oUsing the 68HC11 as the output device (to the printer) requires a software interface (note the errors in the text!)

29. Handshaking I/O

31. ; Listing 9.16 ; I/O service routines to control "Centronics" interface ; part of printer control system. Also demonstrates ; software handshaking because port C configured ; for simple input strobe. Main program would call ; service routines to store input data in a RAM print ; buffer for later output to print mechanism. ;;; CONNECTIONS ; Computer Printer Port MCU as Printer Controller ; DATA -----------------> Port C ; STB -----------------> STRA ; ACK <----------------- PD2 ; BUSY <----------------- PD3 ;; Contd …

32. Handshaking I/O PIOC CONFIGURATION DETAILS ; INVB=x STRB not used ; EGA=0 STRA/ACK active on falling edge ; PLS=x Pulsed/Interlocked not used ; OIN=x Output/input handshake not used ; HNDS=0 Simple strobe mode ; CWOM=0 Normal CMOS outputs ; STAI=0 Disable interrupt ; STAF=x Sets on falling STRA line ; To clear STAF, read PIOC, then read PORTCL Contd …

33. Handshaking I/O ORG $100 ; Subroutine INIT_INTRF ; Initializes parallel interface part ; of printer upon power-up reset. ; Calling Registers: ; IX = Address of register block ; No Return Registers except CCR affected Contd …

34. Handshaking I/O INIT_INTRF: psha ; preserve registers ldaa PIOC,X ; clear STAF if set Ldaa PORTCL,X bset PORTD,X $0C ; PD2, 3 output and bset DDRD,X $0C ; BUSY, ACK high ldaa #00 ; configure PIOC staa PIOC,X pula ; restore registers rts ; and return Contd …

35. Handshaking I/O ; Subroutine INPUT ; Reads parallel port to get byte sent ; by an external device ; Calling registers ; IX = Address of register block ; Return registers ; ACCA = input data byte ; CCR affected Contd …

36. Handshaking I/O INPUT: bclr PORTD,X $0C ; BUSY low and pulse ACK nop ; for approx 5 us (E=2MHz) bset PORTD,X $04 ; set ACK high again CIN: brclr PIOC,X $80 CIN ; wait for STB pulse ldaa PORTCL,X ; get input and clear STAF bset PORTD,X $08 ; set BUSY high rts ; return

37. Parallel subsystem summary oPorts B and C are available for I/O only in the single chip mode -- can be replaced by the PRU when in expanded mode oPort A o3 input, 3 output, 2 bi-directional pins oBits DDRA7 and DDRA3 in PACTL set direction for A7 and A3 oPort B oParallel output only (single chip mode) Contd …

38. Parallel subsystem summary oPort C oData register is PORTC oLatched register is PORTCL oEach bit is bi-directional oDirection set using register DDRC oPort D o6 bi-directional pins, directions set by DDRD oPin 6 = STRA, Pin 7 = STRB oThese pins become AS and R/W* in expanded multiplexed mode Contd …

39. Parallel subsystem summary oPort E o8-bit input only oConditions on reset oAll data direction bits set to 0 (input) oOutput port bits set to 0 oInput port bits high impedance Contd …

40. Parallel subsystem summary oStrobed I/O oStrobed output via Port B, strobed input via Port C oDetected edge on STRA causes input data to be latched in PORTCL and flag set (and interrupt, if enabled) oWriting data to Port B also pulses STRB oHandshake I/O oPort C used for either input or output operation oInput: read data from PORTCL oOutput: write data to PORTCL