1. Ch.7 Layout Design Standard Cell Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology

2. Layout Design Gate Level Simulatior Layout Design Netlist Mask Data Layout Netlist DRC/LVS Functional Verification ATPG Test Pattern

3. Layout Procedure Floorplaning Placement Clock Tree Generation Routing Whole picture Assign standard cells on a column in a row so as to minimize the total wiring lengths. Inverters are inserted Clock Distribution Not to get clock skew Assign interconnection wires to tracks in routing channels.

4. 7.1 Floor Planning

5. 1.Floor Planning Floorplanning is chip-level layout design. Blocks or cells of a variety of shapes and sizes, estimated. Purpose is to derive interface requirement and to estimate budget for each block design.

6. Standard Cell Floor Plan

7. Cell Model

8. 7.2 Placement

9. Min-cut Placement Step 1. Cut the placement area into two pieces. Step 2. Swap the logic cells to minimize the cut cost. Step 3. Repeat the process from step 1, cutting smaller pieces until all the logic cells are placed. (a) Divide the chip into bins using a grid. (b) Merge all connections to the center of each bin. (c) Make a cut and swap logic cells between bins to minimize the cost of the cut. (d) Take the cut pieces and throw out all the edges that are not inside the piece. (e) Repeat the process with a new cut and continue until we reach the individual bins.

10. Placement Result

11. Filler Cell The purpose of filler cells is to maintain continuity in the rows by adding vdd! and gnd! lines and an n- well. The filler cells also contain substrate connections to improve substrate biasing.

12. 7.3 Timing and Clock

13. Timing Problem t d : Longest path through combinational logic t skew : Clock skew t su : Setup time of the synchronizing elements t ds : Propagation delay within the synchronizing element

14. Zero Skew Routing 1.FF Clustering Adjacent FF into the same cluster Load balance among clusters Limit to the maximum load 2.Buffer insertion Zero skew joint by bottom up 3.Equi-delay clock tree rou ting Binary Tree by bottom up

15. Clock Insertion Algorithm 1.Cluster a group of close FFs 2.Binary tree routing for clusters 3.Insert optimum number of buffers at bifurcation points. 4. Equi-distant routing in each cluster.

16. 1. Cluster Routing

17. 2. Buffer Insertion for Zero Skew

18. 3. Equi-distant routing in Cluster

19. 7.4 Routing

20. 2015/5/620 Routing

21. Channel Router for Standard Cells 1.Global Router 2.Channel Router 3.Switch Box Wiring

22. Simple Channel Routing Horizontal constraint do not assign overlapping nets into the same horizontal track Horizontal constraint graph Color nodes with the minimum number with different colors for nodes which has edge between them.

23. Vertical constraint graph The direction of edge indicates that the track number of the node with outgoing edge must be younger than nodes with incoming edge

24. Optimum under assumption that only one horizontal wire segment per net. Left-edge channel routing Channel that cannot be routed by the left edge algorithm (Vertical constraint) A dogleg wire

25. Layout after Routing

26. 7.5 Pad

27. 5. I/O Architecture

28. Output design Output Pad

29. Input Pad ElectroStatic Discharge (ESD) Protection npn tr. limits VSS-0.7V pnp tr limits VDD+0.7V Input Pad

30. Pad Layout Design

31. 7.6 Package

32. Packages Before bonding

33. DIP (Dual in-line) PLCC (plastic leadless chip carrier) PGA (Pin Grid array) TAB (Tape Automated Bonding) Packages