1. Week #2 Slides

2. Agenda Recap 15 Years of Evolution to Virtex Four generations of Spartan Project discussion Questions

4. XC2000 Family – The Original

5. First Configuration Logic Block

6. First IO Cell Note: having All user pins be I/O was a big DEAL!!!

7. XC3000 Family CLB Second Generation

8. XC3000 Fabric Array Little black dots Are PIPs

9. XC3000 IO Cell

10. XC4000 CLB Third Generation

11. XC4000 IO Cell Note

12. VIRTEX The Fourth Generation NOTE: VIRTEX Equated with Having hard Fixed blocks Embedded in The fabric

14. … which brings us to Spartan 3 (uh, we did skip a bunch of stuff, but the progression for our needs works out...)

15. Spartan 3 Xilinx and the industry track silicon technology – XC2000 @1.5 micron – XC3000 @ 1 micron – XC4000 @ 0.8 to 0.35 micron – Virtex @ 0.25 micron, V-II @ 0.18-0.13 micron – Spartan 3 & Virtex 4 @ 90 nm – Virtex 5 @65 nm – Spartan 6 @ 45 nm – Virtex 6 @ 40 nm – Etc.

16. Spartan Philosophy Offer a more cost effective solution for higher volume markets Need to reduce costs to do that – Trim features – Reduce test cost – Sacrifice speed over die size – Cheaper packages – Etc. Spartan is the overall result

17. Spartan 3 Family Chart

18. General Architecture

19. Package Migration

20. IO Banks

21. Spartan 3 IO Cell Note

22. Heterogeneous Logic Cells

23. Stuff in Black & Grey Common to SliceL & sliceM Blue stuff in SliceM only

24. Some Block RAM Detail

25. Multiplier Blocks

26. Digital Clock Managers

27. Clock nets Do heavy lifting Different nets In each family FYI

28. Hierarchical Routing

29. Adjust the mix: Spartan 3E

30. Reduce the Banks: more IO pins available

31. Spartan 3E IO Cell Note

32. Adjustable Input Delay

33. Adjust the mix: Spartan 3A

34. Stack the Flash: Spartan 3AN A Single Chip Solution

35. Internal SPI Flash

36. Add a block: Spartan 3A DSP

37. Spartan 3A DSP Architecture

38. DSP48 with a Pre-Adder

39. The Project...

40. Projects Depend On your knowledge Your skill level Your confidence Your interest Uh...I don’t know any of the above points about you! Only YOU know where you are at on this continuum My goal is to get you to where you can design on Xilinx FPGAs, which has a LOT to do with the S/W!

41. Some Ideas Interfaces – MIX & MATCH things Buses and memories Peripherals & memories Buses & peripherals Processors & the above Systems – Build single function items – Combine two or more items – Invent something new

42. Ahh, the Good Old Days... Basic idea: Create useful, correct standard functions then... HOOK ‘EM UP!

43. More

45. Still More

46. Yet Another

47. My All Time Favorite Part

48. Ahh, the Good NEW Days!

49. Graphic stolen from Doug Smith’s Book cover...I’m looking for the CD that was optional

50. Stolen From Smith Like Old TTL Manual

51. Uh, also stolen from Smith... NOTE!!!!

52. Modern Way to Design... Follow the LIGHT!!

53. The Light

54. Possible Projects The Light bulb area has design templates for both VHDL and Verilog I’d like to expand the documentation on them along the lines of the TTL Catalog, and Doug Smith’s book. Need volunteers to take say 10 of the templates, instantiate into a design, capture the schematic (automatic) and simulate to verify the operation

55. Possible Project Continued The Deliverable would be a WORD file organized to have: – Template code – Graphic – Simulation I can make these available to the rest of the class and to future classes

56. Another Idea The Digilent NEXYS2 board is supported by VHDL solutions, which are available. Most of them are 1-2 sheets of code. I’d like to get them in Verilog, with simulations and compiled onto Xilinx Spartan 3 parts. Take a look at the “pmod” code chunks

57. One more thing to remember Your project should you obtain your goal for this class – May be to log some credit to a credential – May be to learn something about FPGAs – May be to design something you always wanted an excuse to design – I won’t know what that is... – It’s up to you