1. Enables simulation of the complete appliedVHDL system without the UART element. UART is removed and a byte I/O interface is used with the SRAM BFM Submission / demonstration instructions SRAM Spec appliedVHDLNoUARTAndRAMBFM ramBFM

2. appliedVHDLNoUARTAndRAMBFM : Assignment instructions ISE Project : appliedVHDLNoUARTAndRAMBFM.ise (provides access to all of the constituent files) 1.appliedVHDLNoUARTAndRAMBFM level appliedVHDLNoUARTAndRAMBFM.vhd VHDL model is provided. Review VHDL code syntax. Do not synthesise. Review appliedVHDLNoUARTAndRAMBFM_TB.vhd VHDL code and stimDat.txt Review appliedVHDLNoUARTAndRAMBFM_TB.udo modelsim macro file. Important note : Loading of a RAMBFM model of 65536 SRAM address is unnecessary and would make simulation impractical. Therefore, when simulating with the RAMBFM, use a 16-element memory index. The RAMBFM memory array size is 16 x 32 bit entries (defined by constant numWords). This requires only 4 SRAM BFM address bits. Use SRAM address limits, provided in the VHDL code template constant msbIndex : integer := 3; -- msb bit index constant msbIndexM1 : integer := 2; -- next lowest bit index For hardware implementation, use 17 and 16 in place of 3 and 2 respectively. The DSP FSM modifies the upper two bits of the SRAM address. Therefore during simulation assign dspRamAdd(17 downto 4) '0'); dspRamAdd(1 downto 0) <= CONV_STD_LOGIC_VECTOR(cnt,2); -- convert to std_logic_vector For hardware implementation, comment out these lines. Simulate appliedVHDLNoUARTAndRAMBFM_TB.vhd. Review the timing waveform and verify correct appliedVHDL system operation. Implementation on FPGA is not required 2.ramBFM Review/verify/complete RAMBFM.vhd (already used at the memCtrlrUnit level)

3. appliedVHDLNoUARTAndRAMBFM_TB simulation