1. Decimal Floating-Point Arithmetic
Dongdong Chen
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2. Objectives
IEEE standard for Decimal Floating-Point (DFP) arithmetic (Lecture 1)
DFP numbers formats
DFP number encoding
DFP arithmetic operations
DFP rounding modes
DFP exception handling
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3. Objectives (Con.)
Algorithm, architecture and VLSI circuit design for DFP arithmetic (Lecture 2)
DFP adder/substracter
DFP multiplier
DFP divider
DFP transcendental function computation
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4. Background
The decimal computer arithmetic went out of style 25 to 30 years ago; no one uses it now." Is that true?
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5. Introduction Decimal is still essential for specific applications
Numbers in commercial databases are decimal
Extensive use decimal in commercial applications
Survey of commercial databases report
Decimal fixed-point or floating-point number
How to process decimal computation
Software computation
Convert back to decimal representation
Problems
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6. Introduction (Con.) Errors from decimal and binary conversion
Example 1: represent 0.1 in DFP or BFP
Decimal representation (BCD code):0.0001
Binary representation: … 0.09…
Example 2: telephone billing Cost: 0.70; Tax: 5%
BFP arithmetic: …8*(1.05)= …
DFP arithmetic: 0.70*(1.05)=0.74
Decimal integer, fixed-point or floating-point?
Decimal hardware or software solutions?
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7. Current Researches DFP arithmetic defined in IEEE 754-2008
IBM computing systems include DFP hardware
IBM Power6, z9, z10
Intel include DFP software solution in system
Intel DFP software computation library
DFP arithmetic IP blocks:
Basic DFP arithmetic IPs:
DFP adder/substrcter, multiplier, divider, square root etc.
Transcendental DFP arithmetic IPs:
DFP CORDIC, Logarithm, antilogarithm, reciprocal etc.
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8. DFP Arithmetic in IEEE 754-2008
Review BFP arithmetic in IEEE
How to define new DFP in IEEE
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9. BFP Floating-point representation
sign, exponent, significand (or mantissa):
(–1)sign × significand × 2exponent
more bits for significand gives more accuracy
more bits for exponent increases range
IEEE 754 floating point standard:
single precision: 8 bit exponent, 23 bit significand
double precision: 11 bit exponent, 52 bit significand
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10. BFP floating-point Number
Leading “1” bit of significand is implicit
Example: if the significand is …0, the actual significand is …0
This is called a normalized number; there is exactly one non-zero digit to the left of the point.
Unique representation of a number
We get a little more precision: there are 24 bits in the significand, but only 23 of them are stored.
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11. Exponent Exponent is “biased” to make sorting easier
all 0s is smallest exponent, all 1s is largest
The actual exponent is e-127 for single precision, and e-1023 for double precision
Bias of 127 for single precision and 1023 for double precision
By biasing the exponent and storing it before the significand, we can compare magnitudes as if they were unsigned integers.
If e = (13110), the actual exponent is =4
If e = (9310), the actual exponent is =-34
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12. BFP Floating-Point Formats
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13. BFP Floating-Point Formats (Con.)
Positive and
negative zero 1
Biased
exponent
Fraction
Positive and
negative infinity ∞
Biased
exponent
Fraction
Positive underflow
Negative underflow
Negative
Overflow
Expressible negative
numbers
Expressible positive
numbers
Positive
Overflow
-2-127
2-127
- (2 – 2-23)×2128
(2 – 2-23)×2128
exponent = 128 and fraction ≠ 0, It is called “not a number” or NaN
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14. (–1)sign×(1+significand)×2exponent – bias
Example
Summary: FP representation
(–1)sign×(1+significand)×2exponent – bias
Example:
decimal: = -3/4 = -3/22
binary: = -1.1 x 2-1
floating point: exponent = 126 =
IEEE single precision:
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15. DFP Number Representation
sign, exponent, significand (or mantissa):
(–1)sign × significand × 10exponent
more digits for significand gives more accuracy
more bits for exponent increases range representation:
DFP formats:
decimal32: DFP storage format encoded in 32-bit
decimal64: DFP computational format encoded in 64-bit
decimal128: DFP computational format encoded in 128-bit
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16. DFP Number format 1-bit Sign (S) is defined as same as BFP format
w+5-bit combination (G) to two subfield:
5-bit (G0…G4) to encode: 2 MSBs of exponent; 1 MSD of significand; Not-a-Number (NaN); Inf;
W-bit(G5…Gw+4) as a suffix 2 MSBs derived from G0…G4, which consists of w+2-bit nonnegative biased exponent.
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17. DFP Exponent Exponent is “biased” to make sorting easier
Binary format (not decimal)
The actual exponent is e-101 for decimal32, e-398 for decimal64, e-6167 for decimal128
Range of exponent is (emin−q+1) ≤ e ≤ (emax−q+1);
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18. DFP Number format (Con.)
J×10-bit Trailing Significand (T) Field:
Densely packed decimal (DPD) encoding
3-digit decimal number encoded to 10-bit binary number
DPD converted to binary coded decimal (BCD)
Binary integer decimal (BID) encoding
decimal number encoded by binary integer
Non-normalized decimal significand
(-1)0 × × (-1)0 × × 101
DFP number’s Cohort
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19. Parameters in DFP Format
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20. Example Summary: DFP representation
(–1)sign×(significand)×10exponent-bias
Convert -8.35×10-2 to decimal64
Sign bit: “1” negative, “0” positive (sign 1)
Exponent: =396 (8-bit “ ”)
Significand: 835(50-bit DPD coding “0… D”)
Encoding of 5-bit MSBs (G0…G4) of Combinational field “01000”
Decimal-64 : “ …..00… ”
“A D” (binary/hex)
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21. DFP special values Not-a-Number: G0…G4 “11111”;
Infinite Number: G0…G4 “11110”, sign of Inf according to the sign bit;
Overflow: If DFP numbers with absolute values are larger than the largest DFP number (|vmax|=(10q - 1)×10emax-q+1) then overflow occurs.
Underflow: If DFP number are less than the smallest DFP number (|vmin|=10emin-q+1) then underflow occurs. If the absolute value of DFP number is less than 10emin and larger than 10emax-q+1, it produces subnormal.
Normal number: The remaining exponent values and significands represent normal numbers.
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22. DFP Arithmetic Operations
Basic DFP arithmetic operations
Two decimal-specific DFP operations
SameQuantum(DFP1,DFP2)
Quantize(DFP1,DFP2)
DFP comparison operations
do not distinguish between redundant of the same number
DFP conversion operations
DFP to BFP conversion (correctly rounded);
DFP to integer conversion
Recommended DFP operations
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23. DFP Arithmetic Operations
Basic DFP arithmetic operations
Two decimal-specific DFP operations
SameQuantum(DFP1,DFP2)
Quantize(DFP1,DFP2)
DFP comparison operations
do not distinguish between redundant of the same number
DFP conversion operations
DFP to BFP conversion (correctly rounded);
DFP to integer conversion
Recommended DFP operations
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24. DFP Number’s Cohort Non-normalized decimal significand
Standard defines the preferred (required) exponent (quantum)
Exact operation results: the cohort member is selected based on the preferred exponent (quantum) for a DFP result of that operation
Inexact operation results: the cohort member of least possible exponent is used to get the maximum number of significant digits
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25. DFP Rounding Modes Five types of active rounding modes
roundTiesToEven
roundTiesToAway
roundTiesToPositive
roundTiesToNegative
roundTowardZero
Correct rounding and Faithful rounding
IEEE require to satisfy the correct rounded results for all DFP arithmetic operations
DFP operations should satisfy all rounding modes
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26. DFP Exception Handling
Invalid operation: Operand is NaN; 0×Inf; quare-root of negative operand; default result is NaN
Division by zero: if the dividend is a finite non-zero number and the divisor is zero. The default result is a +inf or −inf.
Overflow operation: if the magnitude of a result exceeds the largest finite number representable in the format of the operation.
Underflow operation: if the magnitude of a result is below 10emin.
Inexact: the correctly rounded result of an operation differs from the infinite precision result.
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27. DFP Addition/Subtraction
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28. DFP Add/Sub Data flow
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29. DFP Addition Step 1: equalize the exponents
add the mantissas only when exponents are the same.
the number with smaller exponent should be shifting its point to the left, and the number with larger exponent should be shifting its point to right.
Rewriting the operand with the smaller exponent could result in a loss of the least significant digits
keep guard digit, round digit, and stick digit for the operand with smaller exponent
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30. DFP addition Step 2: add the mantissas 0099999x101 +0016234x10-3
Step 3: Normalize the result if necessary
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31. DFP addition Step 4: Round the number if needed
x100 = x100
Step 5: Repeat step 3 if the result is no longer normalized
The final result is
The correct answer is
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32. Guard bits
To help minimize rounding problems, IEEE specifies that intermediate steps of operations must store guard digits - additional internal digits that increase the precision of the operations.
Previous example: add one extra digit.
IEEE requires one guard digit, one rounded digit and one sticky digit to make rounding more accurate.
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33. DFP add/sub
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34. General Description: Addition
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35. Example: Addition
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36. Example: Addition (Con.)
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37. DFU: IBM POWER6 and Z10
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38. High performance Implementation
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39. High performance Implementation
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40. High performance Implementation
[12] A. Vázquez and E. Antelo“A High-performance Significand BCD Adder with IEEE Decimal Rounding” ARITH19, Portland. June
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41. Evaluation Results and Comparison
[Proposed]: A. Vázquez and E. Antelo“A High-performance Significand BCD Adder with IEEE Decimal Rounding” ARITH19, Portland. June
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42. DFP Multiplication
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43. Scheme of decimal multiplier
x : ×
y : =
xy0: x
xy1: x −x
xy2 : x
xy3: 10x
−2x
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44. Partial product generation
Generate XYi
Yi {1,2,3…7,8,9}
XYi is carry save format
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45. Partial product generation
Solid Circles: BCD Sum (digit)
Hollow Circles: Carry (bit)
n-digit radix-10 CSA
m-digit radix-10 counter
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46. Carry Save Adder Tree CSA Tree to Generate Multiplication Result
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47. Flowchart of DFP Multiplier

48. Architecture of DFP Multiplier

49. Exception Detection & Handling
Invalid operation
sNaN (pass significand of sNaN)
0 x ∞ (produce qNaN with significand 0)
Overflow (and Inexact)
IEIP – SLA > Emax
Increase SLA until all LZs removed
Underflow (and possibly Inexact)
IEIP – SLA < Emin
Decrease SLA until 0, then shift right
Inexact

50. Implementation Highlights
Leverage operands' LZCs
SC, SLA, and IESIP
Handle NaNs with minimal overhead
No dataflow modification
Coerce multiplicand or multiplier to 1
Support gradual underflow
Simply extend number of iterations
Simple, control-based rounding scheme

51. Synthesis Results 64-bit (16 digit) operands, DPD encoded
LSI Logic's gflxp 0.11um CMOS, 55ps FO4
Synopsys Design Compiler
Results
Fixed-point 119,653 um FO4s
Floating-point 237,607 um FO4s
Critical path
Fixed-point 4:2 compressor (accumulator)
Floating-point 128-bit barrel shifer

52. Applicability to Parallel Designs
IE and IP shift generation
Rounding scheme
NaN handling
Exception detection and handling
On-the-fly sticky bit generation... NO

53. Sequential vs. Parallel
Less area
Potentially better cycle time
Parallel
Less latency
Higher throughput

54. DFP Division
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55. DFP Division Data Flow Unpacking Decimal Floating-Point Number
Check for zeros and infinity
Subtract exponents
Divide Mantissa
Normalize and detect overflow and underflow
Perform rounding
Replace sign
Packing
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56. Unpacking and Sign Logic
Step1: Unpacking Floating-Point Number Check for zeros and infinity (if F=0, Stop)
Step2: Sign Process
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57. Exponent Subtraction
Step3: Exponent Subtract
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58. Mantissa Division Algorithms Choose here? 1. Restoring division
2. Non-restoring division
3. High-Radix division
4. Convergence division
Step4: Mantissa Division
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59. Normalization
Step5 : Left shift over one bit is needed to make Mantissa result Normalized, also need to detect overflow and underflow
For example: “0934… ” Left shift one bit 
“934… Should tell exponent and Ea=Eb-1
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60. Rounding and Packing
Step6 : Truncate, Round-up, Round-to-nearest. Sometimes, the Rounding Policy above is not fair, according to IEEE Rounding standard: “Round to nearest even” is more better.
Step7: Packing the Sign bit and Exponent bits and Significand bits together, detect the NaN, Infinity,
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61. High performance Implementation
[1] L.-K. Wang and M. J. Schulte, “Decimal Floating-Point Division Using Newton-Raphson Iteration,” Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp , Sep
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62. High performance Implementation
[2] Tomás Lang and Alberto Nannarelli, “A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture,”IEEE Transactions on Computers, pp727–739, IEEE, June 2007.
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63. High performance Implementation
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64. Evaluation Results and Comparison
DFP Divider[1]
DFP Divider[2]
Precision (digit)
16 (decimal64)
Cycle time (ns)
0.57 1
# of cycles
150 20
Latency (ns)
85.5
1: Synthesized with a STM 90-nm standard cell library
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65. DFP Transcendental Arithmetic
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66. Contents Introduction Decimal Logarithmic Converter
Decimal Antilogarithmic Converter
Conclusions
Future Work
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67. 32-bit DFP Logarithm coefficient is a non-normalized decimal Integer.
Example:
To guarantee a 32-bit DFP Calculation, there need to keep 14-digit FXP logarithmic calculation.
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68. 32-bit DFP Antilogarithm
Here:
For 32-bit DFP:
Example:
To guarantee a 32-bit DFP calculation, there need to keep 8-digit FXP antilog calculation.
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69. Digit-Recurrence Algorithm (Log)
The corresponding recurrences:
Here:
ej ∈｛ …0 1…7 8 9｝
selected so that
converges to 1
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70. Digit-Recurrence Algorithm (Antilog)
Any 7-digit fixed-point decimal input N:
The corresponding recurrences:
Here:
selected so that
converges to 0
ej ∈｛ …0 1…7 8 9｝
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71. Selection By Rounding (cont.)
A scaled remainder is defined as:
Log:
Antilog:
is achieved by Rounding W [j]
e1 is achieved by using look-up table, e2…ej can
be obtained with selection by rounding
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72. Architecture: Decimal Log Converter
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73. Implementation Results
Logic Utilization
Used
Available*
Utilization
# of Occupied Slices
2842
13696
21%
Maximum Frequency
47.7 MHz
# of Clock Cycles
17 clock cycle
*: Xilinx Virtex2p XC2VP30 with package ff1157 and speed -7
Critical Path Detail (ns):
Reg2
Mux2
Mult 2
Shifter
Mux5
CLA
Round
Total
1.188
1.564
9.347
1.438
1.350
5.519
0.566
20.97
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74. Architecture: Dec. Antilog Converter
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75. Implementation Results
Logic Utilization
Used
Available*
Utilization
# of Occupied Slices
2315
13696
17%
Maximum Frequency
51.5 MHz
# of Clock Cycles
11 clock cycle
*: Xilinx Virtex2p XC2VP30 with package ff1157 and speed -7
Critical Path Detail (ns):
Reg6
Mult
Mux4
Shifter
CLA
Round
Total
1.599
7.839
1.539
1.100
6.794
0.545
19.42
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76. Comparison (with Binary FXP Log and Exponential Converters)
similar dynamic range for the normalized coefficients.
Binary reference available having the same digit-recurrence algorithm with Selection by Rounding.
The radix-10 is close to radix-8.
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77. Comparison (cont.) (with Binary FXP Log and Exponential Converters)
Radix-10 Decimal1
Radix-8 Binary [1]
Log.
Exp.
Precision (digit) 7 16 24 53
Area (fa2)
1630
2640
1370
2260
647
1829
627
1777
Cycle time (T3) 17 19 18 8
# of cycles 11 21
Latency (T3)
136
323
128
306 56
144 77
168
1: Synthesized with a TMSC 0.18-um standard cell library
2: the area of 1-bit full adder
3: the delay of 1-bit full adder
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78. Conclusions
Achieved 32-bit DFP accuracy of decimal log and antilog results.
Implemented them on FPGA and ASIC.
Compare them with binary converters.
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79. Decimal Log and Antilog Converters
Future Work
The 64-bit and 128-bit DFP logarithm and antilog converters.
The presented architecture can be optimized to achieve a faster speed or occupy a smaller area.
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EE990 April. 2009
Decimal Log and Antilog Converters
79/18 79

80. Summary IEEE 754-2008 defines a DFP standard that defines
number representation in several precisions
correct DFP arithmetic operations
rounding modes
Implementation of DFP Adder, Multiplier, Divider, Logarithmic and Antilogarithmic Converter
Implementing and programming DFP are both really hard.
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