1. R&D for ECAL VFE technology prototype -Gerard Bohner -Jacques Lecoq -Samuel Manen LPC Clermond-Ferrand, Fr -Christophe de La Taille -Julien Fleury -Gisèle Martin LAL Orsay, Fr Presented by Bernard Bouquet ECFA-DESY Workshop Amsterdam April, 2 nd

2. Specifications  Silicon-Tungsten calorimeter  40 layers  30 Millions channels General information  1 train every 200ms  3000 bunch crossing/train  1 bunch crossing every 154ns Timing information  Dynamic range : 15 bit  Auto-triggered front end electronic Signal information  Electronic in the detector : -Thin design for room saving -Low consumption design mechanic information General specifications Electrical specifications

3. Specifications  1 MIP  6.5fC  Linearity below 1% up to 2500 MIP  14 or 15 bit dynamic range Dynamic range  Depending on the silicium wafer size  Assuming 1 chip per wafer  36 diodes per wafer at this point  36 channels per chip Number of channels/chip  1 MIP  40,000 e -  Noise expected to be below 2000 e - Noise specification  Detector is active only 1ms per 200ms  Electronic enabled 2% of total inter-train time Consumption specification General specifications Electrical specifications

4. Schema Block Ch.1 1 10 100 Ch.2 3 BCID 12 ADC Energy BCID Gain Channel selection Channel 6 Ch.36 First ideas on block schema Further ideas on system design

5. Schema Block First ideas on block schema Further ideas on system design  1 ADC/channel ?  Consumption of ADC have to be < 1 mW  Memorize after digitisation  Use of digital memory instead of analogue ADC  New technology  AMS 0.35µm BICMOS  Using standard filter is not possible anymore due to technological problem  high value resistance are not makable anymore  LPC solution :  A switchable integrator Shaper  LPC Will study digital memories +counter :  Static memory  Dynamic memory Bunch crossing counter

6. Preamplifier  Integration of the charge Due to a feedback capacitance  Low noise, high speed design Charge preamplifier Compensation capacitors Middle stage Input stage Feedback capacitor Feedback resistor Output stage OUT 50 1 1

7. Shaper OPA Standard CRRC structure Integration time (switch on) AMS 0.35µm BICMOS techno Does not allow us to choose this solution (R2 ~ 100k) Voltage to current converter Preamp output R1 R2 C1 C2 Standard bandpass filter optimized to minimize noise Structure tested at LPC

8. ADC Structure tested at LPC : PIPELINE ADC  If V IN > V ref  Bit N out =1 and V IN N+1 =(V IN -V ref )*2  If V IN < V ref  Bit N out =0 and V IN N+1 =V IN *2 Behaviour Comparator V ref V IN Amplifier Gain=2 V ref Gnd Bit N out To V IN stage N+1 Stage N of pipeline ADC block schema Chip should be sent to foundry in April 2003 V IN b0b0 b1b1 b2b2 b3b3 b4b4 b5b5 b6b6 b7b7 b8b8 b9b9 10 bit ADC  10 stages

9. Schedule Input transistor Preamplifier 1 analogue channel LAL Foundry of pipeline ADC V  I conversion Integrator shaper LPC This year (depending on funding)