1. The Performance of Polar Codes for Multi-level Flash Memories
Yue Li
joint work with
Hakim Alhussien, Erich F. Haratsch,
and Anxiao (Andrew) Jiang
March 10th, 2014

2. NAND Flash Memory The circuit board of a SSD … Blocks 4 pages/WL
Let us first look at flash memories.
A flash memory chip, for instance, like the one used in the circuit board of a solid state drive, is consisted of many blocks. *
Each blocks consists of many pages * In the figure at the bottom, each row is a page.
So a page then has several transistors*
1 block has 128 pages. One page has 4 KB. So 1 block = 512 KB. 1 plane may have 1024 blocks.
4 pages/WL

3. Multi-Level Cells Four different kinds of pages: Lower even Lower odd10 00 01 11
2 bits/cell
Four different kinds of pages:
Lower even
Lower odd
Upper even
Upper odd
In the early stage of NVMs, single level cells are widely used. A single level cell has two levels, and thus can store 1 bit data.
Data are read out by comparing with predetermined thresholds.
For flash memories, we measure the cell voltage and compared with threshold voltage.
For PCM, we measure the resistance.
To further increase storage density, multi-level cells are used. A multi-level cell has more than 2 levels. And thus can store more than 1 bit data.
For instance, the one being shown on the right is a MLC with 4 levels, storing 2 bits.*
Unfortunately, trade-off always exists. Compared to SLC, MLC will be less reliable. In a recent study, it was shown that the reliability decreases exponentially with number of cell levels for NAND flash.
This is simply because when more levels are programmed into a cell, the gap between two adjacent thresholds are much smaller, therefore, it is easier for noise to change a cell change from a level to an adjacent level for MLC.

4. Why Polar Codes? Desire for optimal ECCs. Excellent properties
Capacity-achieving
Theoretical guarantee of error floor performance
Efficient encoding and decoding algorithms

5. Encoding G Frozen bits Information Bits Input User Bits Polar Codeword
Flash channels
Frozen
Channels
Frozen bits
Noisy Codeword G
Information Bits
Erdal Arıkan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," IEEE Transactions on Information Theory, 2009.

6. Successive Cancellation Decoding
Frozen
Channels
Estimated user bits
Noisy Codeword
Erdal Arıkan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," IEEE Transactions on Information Theory, 2009.

7. Successive Cancellation Decoding
Frozen
Channels
Estimated user bits
Noisy Codeword
Erdal Arıkan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," IEEE Transactions on Information Theory, 2009.

8. Successive Cancellation Decoding
Frozen
Channels
Estimated user bits
Noisy Codeword
Erdal Arıkan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," IEEE Transactions on Information Theory, 2009.

9. Is polar code suitable for flash memories?1
Make polar code work in flash memory 2
Performance evaluations 3
Adaptive decoding

10. Code Length Adaptation
Polar codes have length N = 2m
The code lengths in flash memory need to be flexible.

11. Shortening M C
Noisy C
K – K’ K’
Est. M
N – K’
K – K’ K’
N – K’

12. (N, K, K’)-Shortened Polar Code
(x1, x2, …, xN-k’+1, …, xN)=(u1, u2, …, uN-k’+1, …, uN) G
(x1, x2, …, 0, …, 0)=(u1, u2, …, 0, …, 0) G ç ç 1 …
(u1, u2, …, uN-k’+1, …, uN) K’ K’

13. Evaluation with Random Data
Pseudo-random Data
(0, 1, 1, 0, …, 1)
(1, 0, 1, 0, …, 1) …
Cycling / Retention
(0, 0, 1, 1, …, 1)
(1, 0, 0, 0, …, 1) …
Not generated by polar encoder

14. Treating Random Data as Codewords
(u1, u2, …, uN) = (x1, x2, …, xN) G-1
Invertible
Input
Channel parameters
Output
Construct codes
Frozen Bits

15. Hard and Soft Sensing P( V | bit = 0 ) LLR = log P( V | bit = 1 )
Reference threshold voltages 11 01 00 10
Cell Voltage
LLR = log
___________________
P( V | bit = 1 )
P( V | bit = 0 )

16. Performance Evaluation2
Performance Evaluation

17. Experimental Setup Construct one polar code for each kind of page.
List successive cancellation decoding [Tal and Vardy 2011]
List size = 32 with CRC
Block length
7943 bits shortened from 8192 bits
Code rates
0.93, 0.94, 0.95
Flash data
obtained by characterizing 2X-nm MLC flash chips
6-month retention

18. Hard and Soft Decoding
Hard Decoding
Soft Decoding

19. Different Block Lengths

20. Asymmetric and Symmetric Errors

21. 3
Adaptive Decoding

22. Code Rate Switching
Is repetitive code construction needed at rate-switching PECs?
BER R2
pec3 R2
pec2 R1
pec1
Correction Capability
PEC

23. Why Code Reconstruction is Not Needed?

24. With and Without Code Reconstruction
Upper odd page
Average

25. Summary On the flash data
Polar codes are comparable to LDPC codes using hard and soft sensing
Larger block lengths do not improve decoding performance a lot
More symmetric, better decoding performance
Repetitive code construction is not necessary for adaptive decoding

26. Future Directions Thank You Error floor performance
Comparing with LDPC decoder with the same hardware latency
Efficient hardware implementations
Thank You