1. May 2007Alon Slapak, Afeka college of 271 DSP: Digital Signal Processors Introduction EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

2. May 2007Alon Slapak, Afeka college of 272 The course and the EE curriculum Hardware Algorithm s Image processing Digital systems Logical design Control systems Digital signal processing DSPVLSI Analog circuits EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

3. May 2007Alon Slapak, Afeka college of 273 Course objectives DSP principles and methodologies: Real time, parallel computing, efficiency Learning the Blackfin DSP platform. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

4. May 2007Alon Slapak, Afeka college of 274 DSP fundamentals Real-time suitability Focusing on frequent operations Parallel computing (parallelism) Low power consumption EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

5. May 2007Alon Slapak, Afeka college of 275 DSP fundamentals: Real-time suitability Use periodic tasks algorithms. Avoid dynamic features: dynamic superscalar execution, data-dependent instruction execution times, etc. Use polling or periodic interrupts. Avoid exceptions, conditional branches or even simple branches. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

6. May 2007Alon Slapak, Afeka college of 276 DSP fundamentals: Focusing on frequent operations Frequent operations are realized in a dedicated hardware machine to gain a Single-cycle operations. For example Euclidian inner product and convolution: MAC (Multiply-Accumulator) Circular buffering Zero-overhead looping There is always a tradeoff between machine cost and benefit - that’s why there is no hardware machine for division. Do Not Divide! EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

7. May 2007Alon Slapak, Afeka college of 277 DSP fundamentals: Parallel computing (parallelism) Pipelining: e.g. the Instructions Cycle: Fetch-Decode-Execute Superscalar: A superscalar architecture executes more than one instruction during a single pipeline stage by pre-fetching multiple instructions and simultaneously dispatching them to redundant functional units on the processor. (WIKIPEDIA) SIMD (Single Instruction Multiple Data): An identical instruction is performed on a set of multiple data items e.g. multi MAC, multi cores, vector processors, etc. A good DSP job is to orchestrate the hardware machines to work more the 80% of the time. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

8. May 2007Alon Slapak, Afeka college of 278 DSP fundamentals: Low power consumption “In portable electronic systems, low power consumption helps minimize size and weight while maximizing the life of the battery between charges. Smaller batteries can be used, further reducing the scale of the system. Lower power also helps keep portable systems from becoming hot during prolonged use.“ (Optimizing power consumption in embedded DSP designs: Techniques and tools for generating power profiles and optimizing power consumption, By Jim Patterson and John Dixon, Texas Instruments,2006) Sleep mode for the core and peripherals: From startup on, the application can idle domains that are not in use, limiting peripheral power consumption to only the I/Os that are needed at a given time. Scale the core voltage and frequency: If the DSP can reduce the core clock rate and the operating voltages, a proportional savings in active power consumption results. Use the DSP's internal memory. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

9. May 2007Alon Slapak, Afeka college of 279 DSP fundamentals Special attention should be given to development of algorithms that take advantage of these fundamentals. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

10. May 2007Alon Slapak, Afeka college of 2710 DSP vs. GPP (General Purpose Processor) GPPDSP Poor - moderate Perfect Real-time suitability High (usually a fan is needed) Low Power consumption 100’s of US$10’s of US$Cost HighPoorVersatility EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

11. May 2007Alon Slapak, Afeka college of 2711 DSP architectures evolution Objective: fast computation of Z = X * Y (one instruction and two operands) Methods: Von Neumann Harvard Architecture Super Harvard Architecture Modified Harvard Architecture Cost Speed EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

12. May 2007Alon Slapak, Afeka college of 2712 DSP architectures evolution: Von Neumann Data and instructions are stored in the same single bank. One access to memory (1 piece of data or instruction) is performed during each instruction cycle. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

13. May 2007Alon Slapak, Afeka college of 2713 DSP architectures evolution: Harvard Architecture Data and instructions are stored in two different memory banks. One access to each of the banks is performed simultaneously during each instruction cycle. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

14. May 2007Alon Slapak, Afeka college of 2714 DSP architectures evolution: Super Harvard Architecture Data can be stored in the instructions block also. One access to each of the banks is performed simultaneously to fetch instruction+data or data+data. An instruction cache mechanism is involved in the second option. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

15. May 2007Alon Slapak, Afeka college of 2715 DSP architectures evolution: Modified Harvard Architecture One single-ported instruction block and one dual- ported data block enable single-cycle Access of 2 Pieces of Data and 1 Instruction. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

16. May 2007Alon Slapak, Afeka college of 2716 ADSP-BF533/532/531 Blackfin 500 & 600 MHz 80KBytes L1 Instruction (16KB Cache) 64KBytes L1 Data (32KB Cache) 16-bit External Bus Interface 16-bit PPI / Video I/O Port 2 SPORTs with I2S support SPI Port UART Port with IrDA® Real-Time Clock & Watchdog Timer On-Chip Voltage Regulator 0.8V to 1.2V VDD Blackfin Core Up to 600 MHz System Interface Unit L1 16-bit External Bus Interface Emulator & Test Control Voltage Regulator Event Controller Watchdog Timer Memory DMA System Control Blocks SPORT0 Peripheral Blocks Real Time Clock PLL SRAM / Cache To 80KB Inst. To 64KB Data SPORT 1 PPI 0 / GPIO UART IrDA SPI0 TIMERS (3) High Speed I/O EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

17. May 2007Alon Slapak, Afeka college of 2717 Blackfin Processor Core Two DAGs, byte addressing Eight 32-bit pointer registers Sixsteen DAG registers,32bit Index, Modify, Length, Base Supports16/32 bit instructions Multi-Issue, 64-bit Instructions Interlocked Pipeline Two 16-bit Multipliers Two 40-bit ALUs Four 8-bit Video ALUs One Barrel Shifter Sixteen 16-bit Math registers /Eight 32-bit Math Registers EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

18. May 2007Alon Slapak, Afeka college of 2718 DSP Speed MIPS million instructions per second MOPS million (mathematical) operation per second MFLOPS million floating-point operation per second MMACS million MACs per second EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

19. May 2007Alon Slapak, Afeka college of 2719 DSP Development Flow Simulation target (without a physical processor) enables you to build, edit, and debug your program, even before a processor is manufactured. Your PC connects to the EZ-KIT Lite evaluation system via a cable, enabling you to monitor processor behavior. JTAG emulator enables application software to be downloaded and debugged from within VisualDSP++. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

20. May 2007Alon Slapak, Afeka college of 2720 DSP Development Flow Mathematical algorithm MATLAB code for Simulation/Validation RT format MATLAB code + Validation with the former stage DSP Simulation + Validation with the former stage DSP Evaluation + Validation with the former stage DSP Emulation + Validation with the former stage EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

21. May 2007Alon Slapak, Afeka college of 2721 C or Assembler Assembler Pros : Maximal efficiency Cons: Required core architecture knowledge Complicated for reading Complicated for writing Long development time Expensive development HR C Pros : Core architecture knowledge is not required Easy for reading Easy for writing Short development time Cheap development HR Maximal efficiency Cons: Limited efficiency (depends on the optimizer) EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

22. May 2007Alon Slapak, Afeka college of 2722 C or Assembler Intensive code parts– Assembler Bureaucracy – C/C++ Algorithms analysis by assembler expert. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

23. May 2007Alon Slapak, Afeka college of 2723 C and C++ Language Programming Motivation: Portability, maintainability, time to market Full ANSI Language –plus: // C++ style comments –other general programmability extensions Full-featured library –full standard math function support –additional DSP functions –basic I/O: printf, simple file I/O Extensions tailored for DSP Highly effective optimizer Fully integrated into programming environment –edit, build support –runtime system in place –source-language debugging EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

24. May 2007Alon Slapak, Afeka college of 2724 BF533 EZ-KIT Lite Block Diagram ADSP-BF533 Blackfin® Processor 32 MB (16M x 16-bit) SDRAM 2 MB (512K x 16-bit x 2) FLASH memory AD1836 96 kHz audio codec w/ 4 input and 6 output RCA jacks ADV7183 video decoder w/ 3 input RCA jacks ADV7171 video encoder w/ 3 output RCA jacks ADM3202 RS-232 line driver/receiver EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

25. May 2007Alon Slapak, Afeka college of 2725 BF533 EZ-KIT Lite Connectors To connect the EZ-KIT Lite board: 1.Plug the provided power supply into J9 on the EZ-KIT Lite board. Visually verify that the green power LED (LED1) is on. Also verify that the red reset LED (LED2) goes on for a moment and then goes off. 2.Connect one end of the USB cable to an available full speed USB port on your PC and the other end to J10 on the ADSP- BF533 EZ-KIT Lite board. LED1 LED2 EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

26. May 2007Alon Slapak, Afeka college of 2726 BF533 EZ-KIT Lite LEDs and Push buttons The EZ-KIT Lite provides four push buttons and six LEDs for general-purpose IO. The six LEDs, labeled LED4 through LED9, are accessed via some of the general-purpose IO pins of flash memory interface. The four general-purpose push button are labeled SW4 through SW7. A status of each individual button can be read through programmable flag (PF) inputs, PF8 through PF11. A PF reads “1” when a corresponding switch is being pressed-on. When the switch is released, the PF reads “0”. A connection between the push button and PF input is established through the SW9 DIP switch. EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home

27. May 2007Alon Slapak, Afeka college of 2727 After the lecture… Download and install the VisualDSP++ from the VisualDSP++ Development Software Test Drive Download For Blackfin Processors: ( http://www.analog.com/processors/blackfin/evaluationDevelopment/blackfinProcessorTestDrive.html ) http://www.analog.com/processors/blackfin/evaluationDevelopment/blackfinProcessorTestDrive.html Download and read the “ADSP-BF533 EZ-KIT Lite® Evaluation System Manual” from the Blackfin Processor Manuals library: ( http://www.analog.com/processors/blackfin/technicalLibrary/manuals/index.html ) http://www.analog.com/processors/blackfin/technicalLibrary/manuals/index.html EZ-KIT Fundamentals Architecture Developmen t flow Introduction At Home