1. Adv. Digital Circuit Design
EE365
Adv. Digital Circuit Design
Clarkson University
Lecture #3
Combinational Logic

2. Combinational-Circuit Analysis
Combinational circuits -- outputs depend only on current inputs (not on history).
Kinds of combinational analysis:
exhaustive (truth table)
algebraic (expressions)
simulation / test bench (example in lab #2)
Write functional description in HDL
Define test conditions / test vecors, including corner cases
Compare circuit output with functional description (or known-good realization)
Repeat for “random” test vectors
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3. Combinational-Circuit Design
Sometimes you can write an equation or equations directly using “logic” (the kind in your brain).
Example (alarm circuit):
Corresponding circuit:
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4. Alarm-circuit transformation
Sum-of-products form
Useful for programmable logic devices (next lec.)
“Multiply out”:
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5. Sum-of-products form
AND-OR
NAND-NAND
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6. Product-of-sums form OR-AND NOR-NOR
P-of-S preferred in CMOS, TTL (NAND-NAND)
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7. Brute-force design Truth table --> canonical sum (sum of minterms)
row N3 N2 N1 N0 F
Brute-force design
Truth table --> canonical sum (sum of minterms)
Example: prime-number detector
4-bit input, N3N2N1N0
F = SN3N2N1N0(1,2,3,5,7,11,13)
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8. Minterm list --> canonical sum
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9. Algebraic simplification
Theorem T8,
Reduce number of gates and gate inputs
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10. Resulting circuit
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11. Visualizing T10 -- Karnaugh maps
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12. 3-variable Karnaugh map
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13. Example: F = S(1,2,5,7)
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14. Karnaugh-map usage Plot 1s corresponding to minterms of function.
Circle largest possible rectangular sets of 1s.
# of 1s in set must be power of 2
OK to cross edges
Read off product terms, one per circled set.
Variable is 1 ==> include variable
Variable is 0 ==> include complement of variable
Variable is both 0 and 1 ==> variable not included
Circled sets and corresponding product terms are called “prime implicants”
Minimum number of gates and gate inputs
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15. Prime-number detector (again)
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16. Prime-number detector (again)
When we solved algebraically, we missed one simplification -- the circuit below has three less gate inputs.
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17. Another example
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18. Yet another example Distinguished 1 cells Essential prime implicants
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19. POS Circle ‘0’s Use DeMorgans to invert the equation
F’ = (W’•Y•X)+(X’•Z’)
F = ((W’•Y•X)+(X’•Z’))’
F = (W’•Y•X)’•(X’•Z’)’
F = (W+Y’+X’)•(X+Z)
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20. POS
Note that the textbook author likes to draw the Karnaugh map for the F’ function, thus you would circle the ‘1’s (where my examples show the F function and ‘0’s are cirlced).
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21. In-Class Practice Problem
Using Karnaugh maps, find the minimal SOP and POS terms for:
F=ΣW,X,Y,Z(0,2,5,7,8,10,13,15)
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22. In-Class Practice Problem
X • Z’
Z • X’
SOP:
POS:
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23. Quine-McCluskey algorithm
This process can be made into a program, using appropriate algorithms and data structures.
Guaranteed to find “minimal” solution
Required computation has exponential complexity (run time and storage)-- works well for functions with up to 8-12 variables, but quickly blows up for larger problems.
Heuristic programs (e.g., Espresso) used for larger problems, usually give minimal results.
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24. Lots of possibilities
Can follow a “dual” procedure to find minimal products of sums (OR-AND realization)
Can modify procedure to handle don’t-care input combinations.
Can draw Karnaugh maps with up to six variables.
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25. Real-World Logic Design
Some applications have lots more than 6 inputs
can’t use Karnaugh maps
Design correctness more important than gate minimization
Use “higher-level language” to specify logic operations
Use programs to manipulate logic expressions and minimize logic.
PALASM, ABEL, CUPL -- developed for PLDs
VHDL, Verilog -- developed for ASICs
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26. VHDL We will be using VHDL for all design projects
We generally won’t be using VHDL to help with minimization, rather as a method to simulate simple logic circuits built with MSI components
The following slides will cover the basic syntax of using VHDL for our purposes
Program usage (e.g., Xilinx Modelsim) and program/circuit testing will be covered in a separate tutorial
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27. VHDL Topics Objectives VHDL History Application Areas Design Units
Entity Descriptions
Architecture Descriptions
Package and Package Body
Configuration
A Range of Design Examples
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28. VHDL Topics Levels of Abstraction Architecture Types Modeling Behavior
Modeling Structure
Examples
Test Benches
Design Process – overview and summary
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29. Objectives Introduce the basics of VHDL.
Gain a level of understanding that allows you to write VHDL code for any design that you could enter using a schematic editor and standard parts.
Develop an appreciation for the ability of VHDL to handle “mixed” designs (structural, dataflow, and behavioral).
Learn VHDL at a level that would allow you to realize your designs in CPLD or FPGA circuits and to test them.
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30. VHDL History VHSIC Hardware Design Language
Very High Speed Integrated Circuit
DoD sponsored development, thus non-proprietary language
Standardized by the IEEE in 1987
IEEE Standard Logic Package (1164) added to handle simulation of practical digital signal values (e.g. high impedance, pull-ups, etc.)
VHDL standard extended in 1993
Additional standards and enhancements continue
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31. Application Areas for VHDL
System Specification
Design Entry (capture)
Simulation
Synthesis (and fitting)
Test Development
Timing Verification
Documentation
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32. VHDL Design Unit
A set of VHDL statements that can be compiled separately and stored in a library for later use.
Five types of design units:
Entity description
Architecture description
Package
Package body
Configuration
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33. Entity Description
Describes the input and output of one module in a system.
Hides the detailed “inner workings” of the module
May be used to describe modules at a very low level (e.g. gate level) as well as an entire system, and all levels in between
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34. Modeling Interfaces Entity declaration
describes the input/output ports of a module
entity name
port names
port mode (direction)
entity reg4 is port ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end entity reg4;
punctuation
reserved words
port type
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35. VHDL-87 Omit entity at end of entity declaration
entity reg4 is port ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end reg4;
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36. Architecture Description
Provides a functional or structural description of an entity.
Each architecture is bound to only one entity – but an entity may be associated with multiple architectures (only one during any given simulation or synthesis).
Multiple architectures allow for early descriptions of module performance without having to design everything in order to begin functional testing.
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37. Package and Package Body
Provides a common place to gather globally used declarations of constants, signals, functions, procedures, components, etc.
Package body contains the VHDL code for any functions or procedures declared in the package.
Contents of a package are made available to other design units via the use statement.
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38. Configuration
Specifies which architectures are to be used for entities.
Always optional; a default configuration is always provided.
Generally not used for synthesis, but for functional simulation.
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39. A Range of Design Examples
A simple, single part design:
One VHDL source file with an entity – architecture pair and a reference to a standard library (e.g. IEEE Standard Logic).
A more complex design:
Multiple source files, each with an entity architecture pair or with a package declaration.
User as well as standard libraries.
May include a configuration file.
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40. Levels of Abstraction
An important characteristic of VHDL that is not shared by earlier, PLD type languages (such as ABEL, CUPL, etc.) is the ability to represent designs at multiple levels of abstraction.
Example – a 16 bit adder could be represented as:
Interconnections of gates
Interconnections of modules (e.g. full adder or 4-bit adder)
A function that performs binary addition on two vectors of bits
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41. Architecture Types Behavioral Dataflow (Register Transfer) Structural
Describes module performance over time, typically in the form of an algorithm.
Ability to synthesize directly is limited.
Dataflow (Register Transfer)
Specifies registers and combinational logic in terms of data flowing from one function to another.
Structural
Specifies the components and their interconnections
HDL equivalent of a schematic
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42. Modeling Behavior Architecture body Behavioral architecture
describes an implementation of an entity
may be several per entity
Behavioral architecture
describes the algorithm performed by the module
contains
process statements, each containing
sequential statements, including
signal assignment statements and
wait statements
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43. Behavior Example architecture behav of reg4 is begin
storage : process is variable stored_d0, stored_d1, stored_d2, stored_d3 : bit; begin if en = '1' and clk = '1' then stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3; end if; q0 <= stored_d0 after 5 ns; q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns; wait on d0, d1, d2, d3, en, clk; end process storage;
end architecture behav;
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44. VHDL-87 Omit architecture at end of architecture body
Omit is in process statement header
architecture behav of reg4 is begin
storage : process begin end process storage;
end behav;
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45. Modeling Structure Structural architecture
implements the module as a composition of subsystems
contains
signal declarations, for internal interconnections
the entity ports are also treated as signals
component instances
instances of previously declared entity/architecture pairs
port maps in component instances
connect signals to component ports
wait statements
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46. Structural Architecture
Components declared in an architecture must be defined elsewhere.
Components may defined as:
an entity-architecture pair in the same VHDL source file,
an entity-architecture pair in another VHDL source file,
an object in another design tool and supplied in a standard file format,
an object in a technology library
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47. Structural Architecture
Each component type must be declared using a component declaration.
The component declaration must match the entity declaration of the module being used.
component component-name
port ( signal-names : mode signal-type;
signal-names : mode signal-type; …
signal-names : mode signal-type );
end component;
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48. Structural Architecture
Each instance of a component must be instantiated by a component statement.
First form uses order of signals matched to the component declaration.
Second form uses port names as listed in the component declaration.
label: component-name port map (signal1, signal2, …, signaln); OR
label: component-name port map (port1=>signal1, port2=>signal2, portn=>signaln):
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49. Structure Example
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50. Structure Example
Include component declarations in structural architecture body
templates for entity declarations
instantiate components
write a configuration declaration
optional, only if more than one architecture is specified for a given entity.
binds entity/architecture pair to each instantiated component
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51. Structure Example
First declare D-latch and and-gate entities and architectures
entity d_latch is port ( d, clk : in bit; q : out bit ); end d_latch;
architecture basic of d_latch is begin
latch_behavior : process begin if clk = ‘1’ then q <= d after 2 ns; end if; wait on clk, d; end process latch_behavior;
end basic;
entity and2 is port ( a, b : in bit; y : out bit ); end and2;
architecture basic of and2 is begin
and2_behavior : process begin y <= a and b after 2 ns; wait on a, b; end process and2_behavior;
end basic;
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52. Structure Example
Declare corresponding components in register architecture body
architecture struct of reg4 is
component d_latch port ( d, clk : in bit; q : out bit ); end component;
component and2 port ( a, b : in bit; y : out bit ); end component;
signal int_clk : bit;
...
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53. Structure Example Now use them to implement the register ... begin
bit0 : d_latch port map ( d0, int_clk, q0 );
bit1 : d_latch port map ( d1, int_clk, q1 );
bit2 : d_latch port map ( d2, int_clk, q2 );
bit3 : d_latch port map ( d3, int_clk, q3 );
gate : and2 port map ( en, clk, int_clk );
end struct;
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54. Mixed Behavior and Structure
An architecture can contain both behavioral and structural parts
process statements and component instances
collectively called concurrent statements
processes can read and assign to signals
Example: register-transfer-level model
data path described structurally
control section described behaviorally
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55. In-Class Practice Problem
We want to write VHDL code for a buffer.
Write an Entity for an Architecture that would take a single binary value, A, as an input, then pass it to the output, W, after 20ns.
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56. In-Class Practice Problem
entity buffer is
port (A : in bit;
W : out bit);
end buffer;
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57. In-Class Practice Problem
Now write the behavioral Architecture
Write an Architecture that would take a single binary value, A, as an input, then pass it to the output, W, after 20ns.
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58. In-Class Practice Problem
architecture basic of buffer is
begin
W <= A after 20 ns;
end basic;
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59. In-Class Practice Problem
Now create another instance of the same entity by writing a similar Architecture that only has a 5ns delay.
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60. In-Class Practice Problem
architecture fast of buffer is
begin
W <= A after 5 ns;
end fast;
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61. Test Benches Testing a design by simulation Use a test bench model
an architecture body that includes an instance of the design under test
applies sequences of test values to inputs
monitors values on output signals
either using simulator
or with a process that verifies correct operation
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62. Test Bench Example Lect #3 Rissacher EE365
entity test_bench is end entity test_bench;
architecture test_reg4 of test_bench is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav) port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );
stimulus : process is begin d0 <= ’1’; d1 <= ’1’; d2 <= ’1’; d3 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns; en <= ’1’; wait for 20 ns; clk <= ’1’; wait for 20 ns; d0 <= ’0’; d1 <= ’0’; d2 <= ’0’; d3 <= ’0’; wait for 20 ns; en <= ’0’; wait for 20 ns; … wait; end process stimulus;
end architecture test_reg4;
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63. Regression Testing Test that a refinement of a design is correct
that lower-level structural model does the same as a behavioral model
Test bench includes two instances of design under test
behavioral and lower-level structural
stimulates both with same inputs
compares outputs for equality
Need to take account of timing differences
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64. Design Processing Analysis Elaboration Simulation Synthesis Lect #3
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65. Analysis Check for syntax and semantic errors
syntax: grammar of the language
semantics: the meaning of the model
Analyze each design unit separately
entity declaration
architecture body …
best if each design unit is in a separate file
Analyzed design units are placed in a library
in an implementation dependent internal form
current library is called work
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66. Elaboration “Flattening” the design hierarchy
create ports
create signals and processes within architecture body
for each component instance, copy instantiated entity and architecture body
repeat recursively
bottom out at purely behavioral architecture bodies
Final result of elaboration
flat collection of signal nets and processes
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67. Elaboration Example
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68. Elaboration Example
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69. Simulation Execution of the processes in the elaborated model
Discrete event simulation
time advances in discrete steps
when signal values change—events
A processes is sensitive to events on input signals
specified in wait statements
resumes and schedules new values on output signals
schedules transactions
event on a signal if new value different from old value
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70. Simulation Algorithm Initialization phase
each signal is given its initial value
simulation time set to 0
for each process
activate
execute until a wait statement, then suspend
execution usually involves scheduling transactions on signals for later times
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71. Simulation Algorithm Simulation cycle
advance simulation time to time of next transaction
for each transaction at this time
update signal value
event if new value is different from old value
for each process sensitive to any of these events, or whose “wait for …” time-out has expired
resume
execute until a wait statement, then suspend
Simulation finishes when there are no further scheduled transactions
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72. Synthesis
Translates register-transfer-level (RTL) design into gate-level netlist
Restrictions on coding style
Some constructs are not synthesizable
Some constructs are synthesized in inefficient ways – better to force the design to a lower, simpler level
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73. Basic Design Methodology
Requirements
Simulate
RTL Model
Gate-level Model
Synthesize
Test Bench
ASIC or FPGA
Place & Route
Timing Model
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74. How we’ll Simulate We won’t worry about writing test benchs
We’ll be using a program called “Wave” (within Xilinx Modelsim) to look at inputs and outputs of the systems we build
A GUI is provided to edit input patterns
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75. More VHDL Help Link on course website Lect #3 Lect #3 Rissacher EE365

76. Next time VHDL tutorial in Computer Lab Quiz
Transistor-Level Logic Circuits
CMOS
TTL
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