1. © IMEC 2010 MIXED SIGNAL RADIATION TOLERANT DESIGN WITH DARE KNUT ASIC

2. © IMEC 2010 OVERVIEW ▸ KNUT ASIC ▸ Mixed Signal Design Flow ▸ Design Analog Blocks ▸ Integration of Analog Blocks ▸ Physical Verification ▸ Conclusions 2 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL)

3. © IMEC 2010 KNUT ASIC ▸ TESAT Spacecom GmbH & Co.KG ▸ UMC 180nm 1P6M + MiM ▸ Mixed Signal ASIC -88 mm 2 -120 I/O -Digital core300K gates -Analog blocksADC (4) DAC (18) I/O (88) 3 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL)

4. © IMEC 2010 MIXED SIGNAL DESIGN FLOW ▸ Digital-on-top approach, based on -Complexity of digital part -Area estimation digital/analog -Number/type of analog blocks -Experience/familiarity with digital flow for DARE ▸ Extra requirements for analog blocks -Floor planning, placement and routing  Additional layers, additional labels, port placement,.. -Timing analysis  Additional simulations 4 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL)

5. © IMEC 2010 DESIGN ANALOG BLOCKS ▸ Current-steering DAC ▸ Capacitive SAR ADC ▸ Analog I/O  Schematic entry + SPICE simulator  Standard available UMC Mixed-Mode PDK  Standard DRC checking  Custom LVS checking  Extra RAD checking 5 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL)

6. © IMEC 2010 DAC SPECIFICATION SpecificationRange Resolution10 bit DNL< 1 LSB INL< 1 LSB Temperature Range-55 °C.. +125 °C Analog Supply VoltageVDDA = 3.3 V +/- 10% Temperature Drift< 10 LSB ILSB low current range1µA.. 6 µA ILSB high current range5 µA.. 30 µA Total Dose100 krad 6 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL)

7. © IMEC 2010 DAC DESIGN 7 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL)

8. © IMEC 2010 DAC LAYOUT IMPLEMENTATION 8 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL) 10b Bin2Thermo (fully digital P&R) Current sources matrix with local level shifter Bias voltage generation

9. © IMEC 2010 ADC SPECIFICATION SpecificationRange Resolution10 bit DNL< 1 LSB INL< 1 LSB Temperature Range-55 °C.. +125 °C Analog Supply VoltageVDDA = 3.3 V +/- 10% Temperature Drift< 1 LSB Input Voltage Range0 < Vin < VFS Full Scale Voltage1.4 < VFS < VDDA Conversion Speed< 1 ms Total Dose100 krad 9 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL)

10. © IMEC 2010 ADC DESIGN 10 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL)

11. © IMEC 2010 ADC LAYOUT IMPLEMENTATION 11 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL) SAR + level shifters (full custom layout) analog switches MiM capacitor array Comparator and reference voltage generation

12. © IMEC 2010 ANALOG I/O ▸ Dedicated 3.3V analog power and ground ▸ Analog input and output ▸ Same protection device used as in digital I/O  Full chip ESD behavior initially not good enough (~ 500 V HBM) due to broken ring  ESD optimization (bulk connections, distances, marker layers) increases performance beyond 2KV HBM 12 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL)

13. © IMEC 2010 INTEGRATION OF ANALOG BLOCKS 13 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL) abstract generator LEF script analog simulation LIB template layout LEF fileLIB file schematic vhdl model description

14. © IMEC 2010 PHYSICAL VERIFICATION ▸ Default checks: DRC, LVS, ANT, ERC ▸ Extra ‘RAD’ check: -Digital layout = standard cell library, well defined flow => correct-by-design/flow -Analog layout = full custom=> prone to mistakes during cell layout or integration on top level -Checks for  NMOS ELT compliance  Presence of guard bands  Forbidden polysilicon routing 14 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL)

15. © IMEC 2010 CONCLUSIONS ▸ KNUT ASIC demonstrates the feasibility of a Mixed Signal design flow for Space Applications with the DARE library ▸ The digital-on-top approach needs descriptions of the analog blocks for doing P&R, STA, IR-drop and power analysis ▸ ESD performance is proven ▸ RAD check gives added value in mixed-mode designs 15 GEERT THYSAMICSA20106 SEPTEMBERESA/ESTEC NOORDWIJK (NL)

16. © IMEC 2010 QUESTIONS ?