1. Chapter 11_1 (chap 10 ed 8) Digital Logic

2. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 2 NOT AND OR XOR NAND NOR Truth Tables Boolean Operators

3. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 3 NOT A = Ā A AND B = A  B A OR B = A + B A XOR B= 1 if and only if one of A or B is 1 A NAND B = NOT ( A AND B) NOR= NOT (A OR B) Truth Tables Boolean Operators

4. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 4 Boolean Algebra Based on symbolic logic, designed by George Boole Boolean expressions created from: – NOT, AND, OR

5. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 5 NOT Inverts (reverses) a boolean value Truth table for Boolean NOT operator: Digital gate diagram for NOT:

6. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 6 AND Truth table for Boolean AND operator: Digital gate diagram for AND:

7. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 7 OR Truth table for Boolean OR operator: Digital gate diagram for OR:

8. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 8 Operator Precedence Examples showing the order of operations:

9. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 9 Truth Tables (1 of 3) A Boolean function has one or more Boolean inputs, and returns a single Boolean output. A truth table shows all the inputs and outputs of a Boolean function Example:  X  Y

10. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 10 Truth Tables (2 of 3) Example: X   Y

11. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 11 Truth Tables (3 of 3) Example: (Y  S)  (X   S) Two-input multiplexer

12. Basic Identities of Boolean Algebra Basic Postulates A B = B AA + B = B + ACommutative Laws A (B + C) = (A B) + (A C)A + (B C) = (A + B) (A + C)Distributive Laws 1 A = A0 + A = AIdentity Elements A = 0A + = 1Inverse Elements Other Identities 0 A = 01 + A = 1 A A = AA + A = A A (B C) = (A B) CA + (B + C) = (A + B) + CAssociative Laws DeMorgan's Theorem

13. De Morgan’s Theorem A NOR B = (NOT A) AND (NOT B) A NAND B = (NOT A) OR (NOT B)

14. Basic Logic Gates

15. NAND Gates

16. NOR Gates

17. Functionally complete set AND, OR and NOT can be implemented fully with NAND gates or NOR gates Thus it is called a functionaly complete set.

18. Sum-of-Products Implementation of Table 11.3

19. Sum of products F = ABC + ABC + ABC

20. Product-of-Sums Implementation of Table 11.3

21. Product of sums (X  Y  Z) = X + Y + Z (De Morgan) 

22. Simplification of Boolean expression Algebraic simplification Karnaugh maps Quine McKluskey Tables

23. Algebraic simplification Show how to simplify F = ABC + ABC + ABC To become F = AB + BC = B(A + C)

24. Impementation of F F = ABC + ABC + ABC

25. Simplified implementation of F = ABC + ABC + ABC = B(A + C)

26. Karnaugh Maps

27. The use of Karnaugh maps

28. Overlapping groups F = ABC + ABC + ABC = B(A + C)

29. The Quine-McKluskey Method

30. 2 nd stage All pairs that differ in one variable

31. Last stage

32. Final stage Circle each x that is alone in a column. Then place a square around each X in any row in which there is a circled X. If every column now has either a squared or a circled X, then we are done, and those row elements whose Xs have been marked constitute the minimal expression. ABC + ACD + ABC + ACD

33. ABCF 0000 0010 0101 0111 1000 1010 1101 1110 Table 11.3 A Boolean Function of Three Variables

34. NAND

35. Multiplexor S2S1F 00D0 01D1 10D2 11D3

36. Multiplexor implementation

37. Decoder

38. Use of decoders To address 1K byte memory using four 256 x 8 bit RAM chips

39. Small-scale integration Early integrated circuit provided from one to ten gates on a chip. The next slide shows a few examples of these SSI chips.

41. Programmable Logic Array (PLA)

43. Read-only memory

44. A 64 bit ROM

45. Binary Addition Truth Tables Table 11.9 Binary Addition Truth Tables

46. 4-Bit Adder

47. Implementation of an Adder

48. Multi-output adder The output from each adder depends on the output from the previous adder. Thus there is an increasing delay from the least significant to the most significant bit. For larger adders the accumulated delay can become unacceptably high.

49. 32-Bit Adder using 8-Bit Adders

50. Carry look ahead