1. 1CADENCE DESIGN SYSTEMS, INC. Using Allegro PCB SI to Analyze a Board’s Power Delivery System from Power Source to Die Pad International Cadence Usergroup Conference September 15 – 17, 2003 Juergen Flamm, Cadence

2. CADENCE CONFIDENTIAL2 About the Author Juergen Flamm Senior Technical Sales Leader Cadence Design Systems Juergen holds a MS EE degree from the “University Fridericiana” in Karlsruhe (Germany) Throughout his career, he has been actively involved at all levels and in all aspects of electronic design. He started designing wideband telephony line amplifiers and repeaters at AEG Telefunken. Next he joined Litef (Litton Germany) as the lead engineer for sensor electronic development. He designed mixed mode analog/digital ASICs, miniaturized hybrid electronics and next level multi- board system in a box electronics. He relocated to the United States in 1990 to join Litton corporate as the leader of an international technology transfer team. Shortly after, he was promoted to manager of the Analog Design Group to move on to manager of the Electronic Engineering Department. With the beginning of 2001, a planned careerr change brought Juergen to Cadence. He joined PSD as a Senior Technical Sales Leader with focus on the Allegro PCB SI family of tools. He holds 5 patents in the areas of performance electronics for fiber optic and MEMS sensors.

3. CADENCE CONFIDENTIAL3 Agenda Introduction Describing the problem Developing a Solution –Step1:Power delivery system analysis for a board using Allegro PCB PI –Step2: Power delivery system analysis for a board/package combination using Allegro PCB SI SSN –Step3: Combining Step1 and Step2 and more Summary Q & A

4. CADENCE CONFIDENTIAL4 Introduction Today’s high speed circuits, operating at fast edge rates ( 100MHz), combined with decreasing supply voltage and increasing supply current demands, have been placing growing challenges on the design of power delivery systems. This presentation will show how Allegro PCB SI can be utilized to perform post-layout analysis of the power delivery system of a completed board design (see ICU 2003 paper #2 for details). Post-layout analysis is only one use model of Allegro PCB SI. The tool’s real power will be experienced when also proactively employed for pre- layout design and analysis as well as for floor planning of a power delivery system. However, these use models are not subject of this presentation.

5. CADENCE CONFIDENTIAL5 Describing the Problem Example: Parasitic elements in the PWR/GND supply path cause power supply noise and fluctuations on the chip supply rails

6. CADENCE CONFIDENTIAL6 Describing the Problem (cont.) Multiple elements must be considered simultaneously when analyzing a board’s PWR/GND path from power source to the chip supply rails. –Board power source (VRM) –Output current slew rate capability, dynamic source impedance, … –Board plane structures –Differential and common mode impedance, resonances, … –Board decoupling capacitors –Type, quantity, pin escape and via connections, placement location, … ---- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ---- –Board traces and associated vias –Interconnecting PWR/GND planes and chip package pins, … –Package model (chip) –Pins, traces, planes, vias, bond wires, …

7. CADENCE CONFIDENTIAL7 Developing a solution Step1 –Analyze a board’s PWR/GND plane pair’s impedance, including decoupling capacitors, using Allegro PCB PI frequency domain simulation. Step2 –Analyze the PWR/GND connection path from planes to the chip power rails using Allegro PCB SI SSN time domain simulation. Step3 –Append Step2 model with Step1 source impedance model. –Use appended model and Allegro PCB SI SSN simulation to evaluate PWR/GND bounce impact on signal waveform and timing.

8. CADENCE CONFIDENTIAL8 Step1 Allegro PCB PI Prepare board for and run Allegro PCB PI frequency domain simulations –Complete Allegro PCB SI “Setup Advisor”, focus on “Identify DC Nets” –Complete Allegro PCB PI “Setup Wizard”, select at least 1 standard library capacitor –Use “Report” to identify capacitor types per plane pair –Create/assign models for/to identified capacitor types –Under “Cap Libraries” in Board Folder and select used capacitor types –Approximate maximum worst case switching current, place noise source –Determine VRM model parameters and place VRM –Set preferences and run multi node simulations –Analyze resulting impedance graphs –Optionally determine a simple worst case source impedance model (R, L, C)

9. CADENCE CONFIDENTIAL9 Step1 Design & Analysis Report Library Setup

10. CADENCE CONFIDENTIAL10 Step1 Board with highlighted Plane Shapes, VRM, Noise Source, Grid Size

11. CADENCE CONFIDENTIAL11 Step1 Multi Node Simulation result Simple source impedance approximation: Z = 40mOhm + j2pi*f*0.32nH

12. CADENCE CONFIDENTIAL12 Step2 Allegro PCB SI -SSN –Prepare board for and run Allegro PCB SI SSN time domain simulations –Use Allegro PCB SI “Setup Advisor”, focus on “Device Setup” and “SI Model assignment” –Check targeted device model for pin parasitic values –Assign power bus to associated power pins of device model –Assign ground bus to associated ground pins of device model –Assign power and ground bus to desired simultaneously switching I/O pins of device model –Select preferences as intended and run Allegro PCB SI SSN simulation to create waveforms

13. CADENCE CONFIDENTIAL13 Step2 Power & ground bus assignments Pin data A large package model instead of pin data could be used to provide a more comprehensive model. Device model preparation

14. CADENCE CONFIDENTIAL14 Step2 Power and ground bounce wave forms

15. CADENCE CONFIDENTIAL15 Step2 Additional signal waveform evaluation options –Extract net into Allegro PCB SI 210 (SigXp) tool, add current probe and perform reflection simulation –Evaluate single net voltage and current waveforms –Helpful to determine/validate rise/fall times and maximum switching current used in step1 –Set up and run EMI simulation –Evaluate single net spectral current distribution –Helpful to determine needed bandwidth for target impedance in step1

16. CADENCE CONFIDENTIAL16 Step2 Extracted net with current probeDriver voltage wave form Driver current wave form Spectral current distribution

17. CADENCE CONFIDENTIAL17 Step3 Allegro PCB SI SSN with added simple source impedance model parameters from Step1 –Use R and L model from Step1 (slide 11) –Divide R and L in half and add the values to each power and ground pin’s parasitic values in the device model. –Other options –Add to large package model parameters –Combine Step1 and Step2 net lists –…

18. CADENCE CONFIDENTIAL18 Step3 Comparison of Allegro PCB SI-SSN simulations with and without additional source impedance model added to pin parameters

19. CADENCE CONFIDENTIAL19 Step3 More –Performing a comparison between Reflection and SSN simulation results. –Evaluate power and ground bounce impact on a signal’s waveform –Evaluate power and ground bounce impact on a signal’s timing –Evaluate …

20. CADENCE CONFIDENTIAL20 Step3 Reflection/SSN simulation comparison Falling edge detail

21. CADENCE CONFIDENTIAL21 Summary Using Allegro PCB SI, we have briefly introduced options to perform post-layout analysis of a power delivery path from power source to the chip supply rails. We have used a three step approach utilizing Allegro PCB PI (SQ-PI) and Allegro PCB SI-SSN options and features of the tool. We have briefly touched on capabilities, which enable the design engineer to perform comprehensive types of simulations. –For example: Simulating the effect of power and ground bounce on signal waveform and timing. Knowing and intelligently utilizing the features and options of Allegro PCB SI can significantly increase a design engineer’s success. –For example: Performing virtual prototyping, pre-layout analysis and floor planning of the power delivery system.

22. CADENCE CONFIDENTIAL22 Q&A Contact information: –Juergen Flamm –Cell phone: 818-642-2633 –Office phone: 818-881-9965 –E-mail: jflamm@cadence.com

23. CADENCE CONFIDENTIAL23