1. 4bit Parallel to Serial Data Stream Converter By Ronne Abat Johnny Liu

2. Agenda Specifications D Flip Flop Test Bench Timing Analysis Fabrication Conclusion

3. Specification 4bit Parallel to Serial Data Converter -At 25Mhz, Period = 40ns -Using Positive Edge Trigger Clock -Registers reset when clear = 0 -Drive a 10pf load -AM16 Process -Power Consumptions lower than 500mW -Area less than 40mm square

4. Top Level Schematic

5. D Flip Flop Schematic

6. D Flip Flop Transient Response

7. D Flip Flop H-L

8. D Flip Flop L-H

9. Write Mode Test Bench

10. Transient Response Write Mode

11. Shift Mode Test Bench

12. Transient Response Shift Mode

13. Layout

14. Conclusion All specs were met except for - extracted - power - timing on serial outputs