1. DAC 2014 - IP Track Submission CDC aware power reduction for Soft IPs Ritesh Agarwal (Freescale™) Amit Goldie (Atrenta) Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.

2. 2 DAC 2014 - IP Track Submission Background and Motivation Need for CDC aware power reduction  Clock gating changes for power reduction that introduce clock domain crossings can lead to chip killer CDC bugs and/or design re-spins. It can anyway lead to increased iterations, last minute ECO fixes and great productivity loss if not detected early in the design cycle The one-pass cdc-aware power reduction flow provides power reduction benefits when developing low-power, high-performance SoCs  Designers using this flow are able to push the bar for reducing excess power on their IPs without worrying about their downstream CDC issues which can go a long way in helping them create power-efficient SoCs SpyGlass® Power leverages already existing SpyGlass® CDC setup (clock domain crossing reports) to generate CDC aware (correct-by-construction) clock-gating changes in the RTL

3. 3 DAC 2014 - IP Track Submission Traditional vs. CDC aware Power Reduction RTL CDC-aware Power Reduction CDC-aware Power Reduction Final RTL Review Clock Setup CDC report Validate CDC Feed CDC info RTL Power Reduction Final RTL Validate CDC CDC Issues Back & Forth iterations to resolve CDC issues CDC report

4. 4 DAC 2014 - IP Track Submission Clock Crossing Issue on Implicit Enable Ck1 Ck2 Ck1 Ck2 ICG Properly synchronized crossing CDC unaware transformation leading to faulty circuit using automated clock-gating to “save power” – breaks functionality! Metastable Point

5. 5 DAC 2014 - IP Track Submission Missing Synchronizer Detection in Power Reduction Some opportunities seem safe… …but may introduce a CDC problem  Any enable generated using meta-stable signal from the synchronizer crossing can lead to clock domain crossing issues in the finally obtained low-power design  Even though we get a low power optimized design using this flow, it may or may not be functionally correct if such type of issues are not caught before hand clk2 EN New enable by backward trace; no domain crossing clk1 clk2 EN Two flop synchronizer Metastable net should not be used for any purpose

6. 6 DAC 2014 - IP Track Submission Enabling CDC-aware Power Reduction Flow Scenario where meta-stable net is suitable for a new enable is uncommon, but not impossible SpyGlass® CDC detects common synchronizers with no additional setup With proper CDC setup, tool can detect any custom/unusual synchronizer such as mux-based, enable-based synchronizers etc SpyGlass® Power can make use of CDC reports to identify low power, CDC safe gating opportunities RTL CDC-aware Power Reduction CDC-aware Power Reduction Final RTL Review Clock Setup CDC report Validate CDC Feed CDC info

7. 7 DAC 2014 - IP Track Submission Out-of-box CDC aware Power Reduction Results CDC-aware power reduction results summary: Benefits of using CDC aware power reduction solution:  Traditional treatment results in 3 clock-domain, 1 convergence issue in the modified RTL  Required additional steps of identifying the incorrect clock gating changes in the RTL which lead to CDC issues  One step CDC aware power reduction flow eliminates the back and forth iterations, producing superior results with productivity gains DetailsCount Total Registers in original RTL26461 Registers with no enable in original RTL1301 Registers with new enable in optimized RTL45 Registers with no enable in optimized RTL1256 Registers with existing enable in original RTL25160 Registers with strengthened enable in optimized RTL4804 Registers with same enable in optimized RTL20356

8. 8 DAC 2014 - IP Track Submission Final Power Reduction Summary Results Original Power (Total) = 20.5mW Modified Power (Total) = 15.9mW Power Savings = 4.6mW (22.5%) Results Validation CDC run on power modified RTL showed zero violations Gate level synthesis on both original and power-modified RTL was done using downstream synthesis tool. No timing issues were found Gate level simulation and power measurement at gate-level yielded around 18% power reduction measured using 3 rd party power estimation tool

9. 9 DAC 2014 - IP Track Submission Conclusion One-pass cdc-aware power reduction flow generates correct-by-construction clock-gating changes in the RTL to deliver smart and reliable power savings Need for several back-and-forth design iterations can be completely avoided using single pass cdc-aware power reduction methodology as described earlier Leads to greater designer confidence on the clock-gating changes recommended by the tool With power efficient IPs, creating low-power, high performance SoCs becomes increasingly viable

10. 10 DAC 2014 - IP Track Submission Future Work Automatically detect reset crossings from existing SpyGlass® CDC reports  Exclude meta-stable reset signals from participating in generation of clock-gating enable logic Not using asynchronous resets as a part of clock-gating enable equations for Observability based clock-gating power reduction changes

11. 11 DAC 2014 - IP Track Submission Thanks