1. Senior Capstone Project GPS Signal Simulator
May 2, 2006
Benjamin Herreid
Anthony Hoehne
Advisor: Dr. In Soo Ahn
Sponsored By:

2. Outline Project Description Block Diagram Software Hardware
System Inputs
GUI Application
Software/Hardware Interface
Hardware
FPGA
RF side
Results and Future Work

3. Project Summary Global Positioning System (GPS)
Satellite based navigation system
Guaranteed worldwide coverage
Solve problem backwards
Generate the simulated GPS signals for up to 4 visible satellites (channels)
Use generated signals to drive a commercial receiver

4. Project Application Model a scenario that uses GPS signals
Useful in developing a GPS receiver
Much cheaper than physical testing
Airplanes
Spacecraft
Tests that are impossible in real life
Repeatability
High-dynamics

5. Equipment PC – Windows XP, Parallel Port FPGA – Altera Cyclone
Altera UP3 Development Board
D/A Converter, OpAmp
MAX5184, 10 bits
LM311
Mixer and Oscillator
RF Signal Generator
Commercial Receiver
Ashtech G8

6. Block Diagram Input data: GUI, Files Data from PC to FPGA
SV Number
Input data: GUI, Files
Data from PC to FPGA
2kHz, Digital
GPS Signal to Mixer
Analog, IF = MHz
Sampling Rate = MHz
GPS Signal to Receiver
Analog, L1 = GHz

7. PC Data Path

8. Trajectory File Proprietary Duration of Jerk
4 axes: Roll, Pitch (Elevation), Yaw (Heading), Thrust
Roll
Pitch
Yaw

9. Initial Conditions 3rd Derivative
Requires initial conditions for lower order parameters
Acceleration: 0
Velocity: 0
Attitude: 0 (level, due North)
Position: Specified by User

10. Almanac and Antenna Files
Almanac File
Standard - Rinex 2
Ephemeris Data
Antenna File
Proprietary
Antenna Gain
Azimuth, Elevation

11. Phase and Visibility Files
Phase File
Phase (distance) to each satellite in radians
At fixed frequency, wavelength is constant so phase and distance are interchangeable (fλ=c)
Visibility File
Azimuth and Elevation of each satellite
Signal Power from each satellite

12. Application Screenshot

13. Application Screenshot

14. PC to FPGA Communication
4 Channels
SVN: 5 bits
Amplitude: 7 bits
Roll Flags: 2 bits
Phase: 18 bits
Total: 32 bits
4 bytes
Byte 1
1 0
Byte 2
Byte 3
Byte 4
Minimum Communication Rate:
4 bytes/channel x 4 channels x 2kHz Update Rate = 32kHz

15. Outline Project Description Block Diagram Software Hardware
System Inputs
GUI Application
Software/Hardware Interface
Hardware
FPGA
RF side
Results and Future Work

16. FPGA Calculations

17. Interpolation Wrapping

18. Signal Spectrum

19. RF Subsystem D/A converter LM311 OpAmp Mixer and signal generator
MAX5184 – 10 bit
40MHz, Differential voltage output
LM311 OpAmp
Conversion to single-ended signal
Mixer and signal generator
Attenuation
-130dBm required for receiver
90dB attenuation needed (-40dBm at D/A)

20. Results PC FPGA RF GUI finished Individual programs run
Data ready for packing
FPGA
Single channel nearly completed
Problems with Quartus II RF
D/A – Not completed
Mixer – Experimented, not implemented

21. Simulations
Interpolation and lookup table indexing

22. Simulations
C/A code generation for SV #1 / Ch 1

23. Future Work Establish Communication Add navigation data
Additional features
Ionosphere and troposphere effects
Multipath
Additional channels (multiple FPGA’s)
Instrument panel in GUI

24. Questions?

25. RF Experimenting