1. ECE2030 Introduction to Computer Engineering Lecture 9: Combinational Logic, Mixed Logic Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

2. 2 Logic Design Logic circuits –Combinational –Sequential Combinational circuits N inputs M outputs Combinational circuits inputs outputs Storage Element delay

3. 3 Combinational Logic Outputs, “at any time”, are determined by the input combination When input changed, output changed immediately –Note that real circuits are imperfect and have “propagation delay” A combinational circuit –Performs logic operations that can be specified by a set of Boolean expressions –Can be built hierarchically Combinational circuits N inputs M outputs

4. 4 Design Hierarchy Example 9-input Odd Function X0 X1 X2 X3 X4 X5 X6 X7 X8 Z A0 A1 A2 3-input Odd Function Z A0 A1 A2 3-input Odd Function X3 X4 X5 A0 A1 A2 3-input Odd Function X6 X7 X8 B0 A0 A1 A2 3-input Odd Function X0 X1 X2 B0 9-input Odd Function How to design a 3-input Odd Function? Function Specification: To detect odd number of “1” inputs, i.e. Z=1 when there is an odd number of “1” present in the inputs

5. 5 Derive Truth Table for Desired Functionality ABCF 0000 0011 0101 0110 1001 1010 1100 1111 00011110 0 0101 1 1010 A BC

6. 6 Design Hierarchy Example 9-input Odd Function X0 X1 X2 X3 X4 X5 X6 X7 X8 Z A0 A1 A2 3-input Odd Function Z A0 A1 A2 3-input Odd Function X3 X4 X5 A0 A1 A2 3-input Odd Function X6 X7 X8 B0 A0 A1 A2 3-input Odd Function X0 X1 X2 B0 9-input Odd Function 3-input Odd function: B0=A0  A1  A2 A0 A1 A2 B0

7. 7 Combinational Logic Design Example B C D A F

8. 8 Mixed Logic Enable component reuse Allow a digital logic circuit designer to implement a combinational logic with –Only NAND gates –Only NOR gates –Only NAND and NOR gates

9. 9 DeMorgan’s Law

10. 10 Mixed Logic (1) Implement all ORs in the Boolean function Implement all ANDs in the Boolean function Forget all the inversion at this moment

11. 11 Example: Mixed Logic (1) B C D A

12. 12 Mixed Logic (2) Draw “Vertical Bars” in the circuits where all complements in the Boolean equation occur Draw a bubble on each Vertical Bar

13. 13 Example: Mixed Logic (2) B C D A

14. 14 Mixed Logic (3) Convert each gate to the desired gate –If only NAND gate is available, insert a bubble in front of the AND gate –If only OR gate is available, insert a bubble in front of the OR gate Using DeMorgan’s Law in the process –OR  NAND: by adding 2 bubbles on the inputs side of OR –AND  NOR: by adding 2 bubbles on the inputs side of the AND

15. 15 Example: Mixed Logic (3) B C D A Assume this design uses NAND gates only =

16. 16 Mixed Logic (4) Balance the bubbles on each wire, i.e. even out the number of bubbles on every wire If there is odd number of bubbles on a wire, add an inverter (i.e. a bubble) And remove those “vertical bars with bubbles” which are used to help only, not in the circuits

17. 17 Example: Mixed Logic (4) B C D A Assume this design uses NAND gates only

18. 18 How about Inverters? Inverters can be implemented by either a NAND or a NOR gate –Wiring the inputs together

19. 19 Example: Mixed Logic (Final) B C D A Assume this design uses NAND gates only

20. 20 Example: Mixed Logic (Final) B C D A Assume this design uses NAND gates only 6 NAND gates are used

21. 21 Mixed Logic How about build the prior circuits with only NOR gates?

22. 22 Example: Mixed Logic (1) B C D A

23. 23 Example: Mixed Logic (2) B C D A Add vertical bar for each inversion

24. 24 Example: Mixed Logic (3) B C D A Assume this design uses NOR gates only = Convert each gate to a NOR

25. 25 Example: Mixed Logic (4) B C D A Assume this design uses NOR gates only Balance number of Bubbles on each wire

26. 26 Example: Mixed Logic (4) Assume this design uses NOR gates only Balance number of bubbles on each wire and substitute all gates to NOR B C D A

27. 27 Example: Mixed Logic (Final) Assume this design uses NOR gates only B C D A 7 NOR gates are used

28. 28 Mixed Logic Example II (1) C D A B Implement the logic circuits by ignoring all inversions

29. 29 Mixed Logic Example II (2) C D A B Add vertical bar/bubble for each inversion

30. 30 Mixed Logic Example II (3) C D A B Assume this design uses NAND gates only

31. 31 Mixed Logic Example II (4) C D A B Balance the bubbles for each wire w/ inverters

32. 32 Mixed Logic Example II (5) C D A B Remove the vertical bars/bubbles

33. 33 Mixed Logic Example II (6) C D A B Replace all the gates to NAND gates

34. 34 Mixed Logic Example II (7) C D A B Final mixed logic uses 11 NAND gates (one of them is a triple-input NAND gate)

35. 35 Mixed Logic Example III (1) B D A C Implement the logic circuits by ignoring all inversions

36. 36 Mixed Logic Example III (2) B D A C Add vertical bar/bubble for each inversion

37. 37 Mixed Logic Example III (3) B D A C Assume this design uses NOR gates only

38. 38 Mixed Logic Example III (4) B D A C Balance the bubbles for each wire w/ inverters

39. 39 Mixed Logic Example III (5) B D A C Remove the vertical bars/bubbles

40. 40 Mixed Logic Example III (6) B D A C Replace all the gates to NOR gates

41. 41 Mixed Logic Example III (7) B D A C Final mixed logic uses 9 NOR gates