1. Dec 21, 2007DfT@IITK1 Design for Testability Virendra Singh Indian Institute of Science Bangalore virendra@ {computer, ieee}.org IEP on Digital System Synthesis at IIT Kanpur (Dec 11-21, 2007)

2. Dec 21, 2007DfT@IITK2 Definition n Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. n DFT methods for digital circuits:  Ad-hoc methods  Structured methods:  Scan  Partial Scan  Built-in self-test (BIST)  Boundary scan n DFT method for mixed-signal circuits:  Analog test bus

3. Dec 21, 2007DfT@IITK3 Ad-Hoc DFT Methods n Good design practices learnt through experience are used as guidelines:  Avoid asynchronous (unclocked) feedback.  Make flip-flops initializable.  Avoid redundant gates. Avoid large fanin gates.  Provide test control for difficult-to-control signals.  Avoid gated clocks.  Consider ATE requirements (tristates, etc.) n Design reviews conducted by experts or design auditing tools. n Disadvantages of ad-hoc DFT methods:  Experts and tools not always available.  Test generation is often manual with no guarantee of high fault coverage.  Design iterations may be necessary.

4. Dec 21, 2007DfT@IITK4 Scan Design  Circuit is designed using pre-specified design rules.  Test structure (hardware) is added to the verified design:  Add a test control (TC) primary input.  Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode.  Make input/output of each scan shift register controllable/observable from PI/PO.  Use combinational ATPG to obtain tests for all testable faults in the combinational logic.  Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.

5. Dec 21, 2007DfT@IITK5 Scan Design Rules n Use only clocked D-type of flip-flops for all state variables. n At least one PI pin must be available for test; more pins, if available, can be used. n All clocks must be controlled from PIs. n Clocks must not feed data inputs of flip-flops.

6. Dec 21, 2007DfT@IITK6 Correcting a Rule Violation n All clocks must be controlled from PIs. Comb. logic Comb. logic D1 D2 CK Q FF Comb. logic D1 D2 CK Q FF Comb. logic

7. Dec 21, 2007DfT@IITK7 Scan Flip-Flop (SFF) D TC SD CK Q Q MUX D flip-flop Master latchSlave latch CK TC Normal mode, D selectedScan mode, SD selected Master open Slave open t t Logic overhead

8. Dec 21, 2007DfT@IITK8 Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF) D SD MCK Q Q D flip-flop Master latchSlave latch t SCK TCK SCK MCK TCK Normal mode MCK TCK Scan mode Logic overhead

9. Dec 21, 2007DfT@IITK9 Adding Scan Structure SFF Combinational logic PI PO SCANOUT SCANIN TC or TCK Not shown: CK or MCK/SCK feed all SFFs.

10. Dec 21, 2007DfT@IITK10 Comb. Test Vectors I2 I1 O1 O2 S2 S1 N2 N1 Combinational logic PI Presen t state PO Next state SCANIN TC SCANOUT

11. Dec 21, 2007DfT@IITK11 Comb. Test Vectors I2 I1 O1 O2 PI PO SCANIN SCANOUT S1 S2 N1 N2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 TC Don’t care or random bits Sequence length = (n comb + 1) n sff + n comb clock periods n comb = number of combinational vectors n sff = number of scan flip-flops

12. Dec 21, 2007DfT@IITK12 Testing Scan Register n Scan register must be tested prior to application of scan test sequences. n A shift sequence 00110011... of length n sff +4 in scan mode (TC=0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output. n Total scan test length: (n comb + 2) n sff + n comb + 4 clock periods. n Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 10 6 clocks. n Multiple scan registers reduce test length.

13. Dec 21, 2007DfT@IITK13 Multiple Scan Registers n Scan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanout pin. n Test sequence length is determined by the longest scan shift register. n Just one test control (TC) pin is essential. SFF Combinational logic PI/SCANIN PO/ SCANOUT MUXMUX CK TC

14. Dec 21, 2007DfT@IITK14 Scan Overheads n IO pins: One pin necessary. n Area overhead:  Gate overhead = [4 n sff /(n g +10n sff )] x 100%, where n g = comb. gates; n ff = flip-flops; Example – n g = 100k gates, n sff = 2k flip- flops, overhead = 6.7%.  More accurate estimate must consider scan wiring and layout area. n Performance overhead:  Multiplexer delay added in combinational path; approx. two gate-delays.  Flip-flop output loading due to one additional fanout; approx. 5-6%.

15. Dec 21, 2007DfT@IITK15 Hierarchical Scan n Scan flip-flops are chained within subnetworks before chaining subnetworks. n Advantages:  Automatic scan insertion in netlist  Circuit hierarchy preserved – helps in debugging and design changes n Disadvantage: Non-optimum chip layout. SFF1 SFF2 SFF3 SFF4 SFF3 SFF1 SFF2 SFF4 Scanin Scanout Scanin Scanout Hierarchical netlist Flat layout

16. Dec 21, 2007DfT@IITK16 Optimum Scan Layout IO pad Flip- flop cell Interconnects Routing channels SFF cell TC SCANIN SCAN OUT Y X X’ Y’ Active areas: XY and X’Y’

17. Dec 21, 2007DfT@IITK17 Automated Scan Design Behavior, RTL, and logic Design and verification Gate-level netlist Scan design rule audits Combinational ATPG Scan hardware insertion Chip layout: Scan- chain optimization, timing verification Scan sequence and test program generation Design and test data for manufacturing Rule violations Scan netlist Combinational vectors Scan chain order Mask data Test program

18. Dec 21, 2007DfT@IITK18 Timing and Power n Small delays in scan path and clock skew can cause race condition. n Large delays in scan path require slower scan clock. n Dynamic multiplexers: Skew between TC and TC signals can cause momentary shorting of D and SD inputs. n Random signal activity in combinational circuit during scan can cause excessive power dissipation.

19. Dec 21, 2007DfT@IITK19 Partial-Scan Definition n A subset of flip-flops is scanned. n Objectives:  Minimize area overhead and scan sequence length, yet achieve required fault coverage  Exclude selected flip-flops from scan:  Improve performance  Allow limited scan design rule violations  Allow automation:  In scan flip-flop selection  In test generation  Shorter scan sequences

20. Dec 21, 2007DfT@IITK20 Partial-Scan Architecture FF SFF Combinational circuit PIPO CK1 CK2 SCANOUT SCANIN TC

21. Dec 21, 2007DfT@IITK21 History of Partial-Scan n Scan flip-flop selection from testability measures, Trischler et al., ITC-80; not too successful. n Use of combinational ATPG:  Agrawal et al., D&T, Apr. 88  Functional vectors for initial fault coverage  Scan flip-flops selected by ATPG  Gupta et al., IEEETC, Apr. 90  Balanced structure  Sometimes requires high scan percentage n Use of sequential ATPG:  Cheng and Agrawal, IEEETC, Apr. 90; Kunzmann and Wunderlich, JETTA, May 90  Create cycle-free structure for efficient ATPG

22. Dec 21, 2007DfT@IITK22 Difficulties in Seq. ATPG n Poor initializability. n Poor controllability/observability of state variables. n Gate count, number of flip-flops, and sequential depth do not explain the problem. n Cycles are mainly responsible for complexity. n An ATPG experiment: Circuit Number of Number of Sequential ATPG Fault gates flip-flops depth CPU s coverage TLC 355 21 14* 1,247 89.01% Chip A 1,112 39 14 269 98.80% * Maximum number of flip-flops on a PI to PO path

23. Dec 21, 2007DfT@IITK23 Benchmark Circuits Circuit PI PO FF Gates Structure Sequential depth Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) s1196 14 18 529 Cycle-free 4 1242 1239 0 3 0 99.8 100.0 3 313 10 s1238 14 18 508 Cycle-free 4 1355 1283 0 72 0 94.7 100.0 3 308 15 s1488 8 19 6 653 Cyclic -- 1486 1384 2 26 76 93.1 94.8 24 525 19941 s1494 8 19 6 647 Cyclic -- 1506 1379 2 30 97 91.6 93.4 28 559 19183

24. Dec 21, 2007DfT@IITK24 Cycle-Free Example F1 F2 F3 Level = 1 2 F1 F2 F3 Level = 1 2 3 3 d seq = 3 s - graph Circuit All faults are testable. See Example 8.6.

25. Dec 21, 2007DfT@IITK25 Relevant Results n Theorem 8.1: A cycle-free circuit is always initializable. It is also initializable in the presence of any non-flip-flop fault. n Theorem 8.2: Any non-flip-flop fault in a cycle-free circuit can be detected by at most d seq + 1 vectors. n ATPG complexity: To determine that a fault is untestable in a cyclic circuit, an ATPG program using nine-valued logic may have to analyze 9 Nff time-frames, where Nff is the number of flip-flops in the circuit.

26. Dec 21, 2007DfT@IITK26 A Partial-Scan Method n Select a minimal set of flip-flops for scan to eliminate all cycles. n Alternatively, to keep the overhead low only long cycles may be eliminated. n In some circuits with a large number of self-loops, all cycles other than self-loops may be eliminated.

27. Dec 21, 2007DfT@IITK27 The MFVS Problem n For a directed graph find a set of vertices with smallest cardinality such that the deletion of this vertex-set makes the graph acyclic. n The minimum feedback vertex set (MFVS) problem is NP-complete; practical solutions use heuristics. n A secondary objective of minimizing the depth of acyclic graph is useful. 12 3 456 L=3 1 2 3 45 6 L=2 L=1 s-graph A 6-flip-flop circuit

28. Dec 21, 2007DfT@IITK28 Test Generation n Scan and non-scan flip-flops are controlled from separate clock PIs:  Normal mode – Both clocks active  Scan mode – Only scan clock active n Seq. ATPG model:  Scan flip-flops replaced by PI and PO  Seq. ATPG program used for test generation  Scan register test sequence, 001100…, of length n sff + 4 applied in the scan mode  Each ATPG vector is preceded by a scan-in sequence to set scan flip-flop states  A scan-out sequence is added at the end of each vector sequence n Test length = (n ATPG + 2) n sff + n ATPG + 4 clocks

29. Dec 21, 2007DfT@IITK29 Partial Scan Example n Circuit: TLC n 355 gates n 21 flip-flops Scan Max. cycle Depth* ATPG Fault sim. Fault ATPG Test seq. flip-flops length CPU s CPU s cov. vectors length 0 4 14 1,247 61 89.01% 805 805 4 2 10 157 11 95.90% 247 1,249 9 1 5 32 4 99.20% 136 1,382 10 1 3 13 4 100.00% 112 1,256 21 0 0 2 2 100.00% 52 1,190 * Cyclic paths ignored

30. Dec 21, 2007DfT@IITK30 Flip-flop for Partial Scan n Normal scan flip-flop (SFF) with multiplexer of the LSSD flip-flop is used. n Scan flip-flops require a separate clock control:  Either use a separate clock pin  Or use an alternative design for a single clock pin Master latch Slave latch D SD TC CK MUX SFF (Scan flip-flop) Q TC CK Normal modeScan mode

31. Dec 21, 2007DfT@IITK31 Random-Access Scan (RAS) PO PI Combinational logic RAM n ff bits SCANOUT SCANIN CK TC ADDRESS ACK Address scan register log 2 n ff bits Address decoder SEL

32. Dec 21, 2007DfT@IITK32 RAS Flip-Flop (RAM Cell) Scan flip-flop (SFF) Q To comb. logic D SD From comb. logic SCANIN TC CK SEL SCANOUT

33. Dec 21, 2007DfT@IITK33 RAS Applications n Logic test:  Reduced test length  Reduced scan power n Delay test: Easy to generate single-input-change (SIC) delay tests. n Advantage: RAS may be suitable for certain architecture, e.g., where memory is implemented as a RAM block. n Disadvantages:  Not suitable for random logic architecture  High overhead – gates added to SFF, address decoder, address register, extra pins and routing

34. Dec 21, 2007DfT@IITK34 Scan-Hold Flip-Flop (SHFF) n The control input HOLD keeps the output steady at previous state of flip-flop. n Applications:  Reduce power dissipation during scan  Isolate asynchronous parts during scan test  Delay testing SFF D SD TC CK HOLD Q Q To SD of next SHFF

35. Dec 21, 2007DfT@IITK35 Delay Test Definition n A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing. n For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic. n Delay test problem for asynchronous circuits is complex and not well understood.

36. Dec 21, 2007DfT@IITK36 Digital Circuit Timing Inputs Outputs time Transient region Clock period Comb. logic Output Observation instant Input Signal changes Synchronized With clock

37. Dec 21, 2007DfT@IITK37 Circuit Delays n Switching or inertial delay is the interval between input change and output change of a gate:  Depends on input capacitance, device (transistor) characteristics and output capacitance of gate.  Also depends on input rise or fall times and states of other inputs (second-order effects).  Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output. n Propagation or interconnect delay is the time a transition takes to travel between gates:  Depends on transmission line effects (distributed R, L, C parameters, length and loading) of routing paths.  Approximation: modeled as lumped delays for gate inputs. n See Section 5.3.5 for timing models.

38. Dec 21, 2007DfT@IITK38 Event Propagation Delays 2 4 6 1 1 3 5 3 1 0 0 0 2 2 Path P1 P2 P3 Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew

39. Dec 21, 2007DfT@IITK39 Circuit Outputs n Each path can potentially produce one signal transition at the output. n The location of an output transition in time is determined by the delay of the path. Initial value Final value Clock period Fast transitions Slow transitions time

40. Dec 21, 2007DfT@IITK40 Singly-Testable Paths (Non-Robust Test) n The delay of a target path is tested if the test propagates a transition via path to a path destination. n Delay test is a combinational vector-pair, V1,V2, that:  Produces a transition at path input.  Produces static sensitization -- All off-path inputs assume non-controlling states in V2. V1 V2 Static sensitization guarantees a test when the target path is the only faulty path. The test is, therefore, called non-robust. It is a test with minimal restriction. A path with no such test is a false path. Target path Off-path inputs don’t care

41. Dec 21, 2007DfT@IITK41 Robust Test Conditions n Real events on target path. n Controlling events via target path. V1 V2 U1 U1/R1 S1 U0/F0 S1 U0 U0/F0 U1/R1 U0/F0 S0

42. Dec 21, 2007DfT@IITK42 A Five-Valued Algebra n Signal States: S0, U0 (F0), S1, U1 (R1), XX. n On-path signals: F0 and R1. n Off-path signals: F0=U0 and R1=U1. S0 U0 S1 U1 XX S0 S0 S0 U0 S0 U0 U0 U0 U0 S1 S0 U0 S1 U1 XX U1 S0 U0 U1 U1 XX XX S0 U0 XX XX XX Input 1 Input 2 S0 U0 S1 U1 XX S0 S0 U0 S1 U1 XX U0 U0 U0 S1 U1 XX S1 S1 S1 U1 U1 U1 S1 U1 U1 XX XX XX S1 U1 XX Input 1 Input 2 Input S0 U0 S1 U1 XX S1 U1 S0 U0 XX AND OR NOT Ref.: Lin-Reddy IEEETCAD-87

43. Dec 21, 2007DfT@IITK43 Robust Test Generation R1 S0 U0 R1 XX S0 U0 F0 U0 Path P3 Test for ↓ P3 – falling transition through path P3: Steps A through E F0 XX A. Place F0 at path origin B. Propagate F0 through OR gate; also propagates as R1 through NOT gate C. F0 interpreted as U0; propagates through AND gate D. Change off-path input to S0 to Propagate R1 through OR gate E. Set input of AND gate to S0 to justify S0 at output Robust Test: S0, F0, U0