1. 5/13/2015 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Built-in Self-test

2. Outline BIST and embedded testing Why BIST Primitive polynomials LFSR Response compression BILBO

3. Define Built-In Self-Test Implement the function of automatic test equipment (ATE) on circuit under test (CUT). Hardware added to CUT: Pattern generation (PG) Response analysis (RA) Test controller Stored Test Patterns Stored responses Pin Electronics Comparator hardware Test control HW/SW ATE PG RA Go/No-go signature Test control logic CK BIST Enable

4. Built-in self-test Disadvantage of LSSD & other scan techniques: 1. Test generation necessary for combinational part 2. Long test time since test have to be shifted in & out 3. Only stuck-at faults are tested - not good for VLSI

5. Built-in self test Test generation is NP complete. This prompted a search for built-in structures * Built-in self test BIST is an alternative to automatic test vector generation * Test generation & verification done by circuits built into the chip * Pseudo-random test vector generation is accomplished by using shift registers

6. Built-in self-test in VLSI Test patterns generated on chip responses to test evaluated on chip external operations only to initialize test & clock go no go results additional pins & silicon area minimized

7. Built-in self test types operation (concurrent or not) test design (exhaustive or not) test vector generation (deterministic or pseudorandom) data compression (full or compresses test vectors)

8. A general built-in self test approach

9. Built-in self test * Deterministic testing identifies test vectors to detect specific faults * Pseudorandom testing detects # of faults by any test vector * Fault coverage increases rapidly at the beginning and slows down towards the end * The response data is compressed using a signature analysis * Linear feedback shift registers (LFSR) used to generate test vectors and compress responses

10. Pseudorandom Integers 0 5 1 3 7 62 4 Start +3 Sequence: 2, 5, 0, 3, 6, 1, 4, 7, 2... 0 5 1 3 7 62 4 Start +2 Sequence: 2, 4, 6, 0, 2... X k = X k-1 + 3 (modulo 8)X k = X k-1 + 2 (modulo 8) Maximum length sequence: 3 and 8 are relative primes.

11. Pseudo-Random Pattern Generation Standard Linear Feedback Shift Register (LFSR)  Produces patterns algorithmically – repeatable  Has most of desirable random # properties May not cover all 2 n input combinations Long sequences needed for good fault coverage eitherh i = 0, i.e., XOR is deleted orh i = X i Initial state (seed): X 0, X 1,..., X n-1 must not be 0, 0,..., 0

12. Pseudo-Random Pattern Generator Various LFSR configurations

13. Pseudo-random Patterns (a)(b) (c) ClkY0Y1Y2Y3ClkY0Y1Y2Y3ClkY0Y1Y2Y3 1001 10011001 111001 01001 1100 211102 00102 0110 301113 10013 0011 410114 1001 50101 60010 71001 Initial state Repeated states Q Q D Q Q D Q Q D Y 1 Y 2 Y 3 Clk Y 0 (c) Q Q D Q Q D Q Q D Y 1 Y 2 Y 3 Clk Y0 (a)

14. Modified LFSR Produces pseudorandom sequence of length 8 ClkY0Y1Y2Y3 Y1’Y2’ 0001 1 110001 211000 311100 401110 510110 60 1010 70 0100 800011 Forcing all possible states in LFSR Initial state

15. Standard LFSR XOR operations performed outside of the shift register

16. Modular LFSR XOR operations performed inside the shift register

17. Linear feedback shift registers Two basic configurations : - internal XOR (IE) - external XOR (EE) Feedback connections based on coefficients of a characteristic polynomial : P(X) = C 0 + C 1 X + C 2 X 2 +…+ C n X n An LFSR with n-flip flops can assume (2 n -1) states with depend upon : initial state, input, and feedback

18. Linear feedback shift registers 1 INTERNAL CONNECTIONS (MODULAR) EXTERNAL CONNECTIONS (STANDARD) P(X) = 1+ X 3 + X 4 XX 2 X 3 X 4 X 4 X 3 X 2 X1 Characteristic Polynomial

19. LFSR Equivalence Q Q D Q Q D Q Q D Y 1 Y 2 Y 3 Clk Y0 (a) P(X)=1+X+X 3 ClkY0Y1Y2Y3Y0Y1Y2Y3 110011001 211001101 311100111 401111110 510110011 601010100 700101010 Q Q D Q QD Q QD Clk Y 1 Y 2 Y 3 Y 0

20. Test generation in BIST LFSR generally works without input - so only the initial state & interconnections decide the next state A generator which generates exactly (2 n -1) different states is called a maximal-length generator All polynomials are either primitive (irreducible) or nonprimitive

21. Test generation in BIST A primitive polynomial generates a max length sequence of test vectors. The number of primitive polynomials of order n grows rapidly with n p - any prime number which divides (2 n -1)

22. Modulo 2 Operations aba  ba+ba+b a-b a - b sumcarrydifference borrow 00 0 0 0 00 01 1 1 0 11 10 1 1 0 10 11 0 0 1 00 Define time translation operation as X k = X (t-k)

23. Math Foundation of LFSR Y j can be represented as:Y j (t) = Y j-1 (t - 1)for j  0 We can express Y j in terms of Y 0 as: Y j (t) =Y 0 (t - j) Denote the translation operator as X k, where k represents the time translation units, thenY j (t) =Y 0 (t)X j On the other hand in LFSR Where the summation is equivalent to an XOR operation. Then we get

24. Math of LFSR Generators From linearity we have and We can then write this expression as Y 0 (t) P N (X) = 0 For non-trivial solutions, Y 0 (t)  0, then we must have P N (X) = 0. Where, P N (X) is called the characteristic polynomial of the LFSR.

25. Primitive Polynomials Examples of primitive polynomials with minimum number of terms NPolynomials 1,2,3,4,6,7,15,221 + X + X n 3,5,11, 21, 291 + X 2 + X n 10,17,20,25,28,311 + X 3 + X n 91 + X 4 + X n 231 + X 5 + X n 181 + X 7 + X n 81 + X 2 + X 3 + X 4 + X n 121 + X + X 3 + X 4 + X n 131 + X + X 4 + X 6 + X n 14, 161 + X + X 3 + X 4 + X n

26. Test generation in BIST For instance for n=8 a minimum polynomial is Example : Let us follow test generation using a primitive polynomial

27. Reciprocal Polynomials The reciprocal polynomial of P(X) is defined by: so P R (X) = X N + C j X N-j for 1  j  N Thus every coefficient C j in P(X) is replaced by C N-j in P R (X) For example, the reciprocal of polynomial P(X) = 1 + X + X 3 is P R (X) = 1 + X 2 + X 3

28. Operations on Polynomials Polynomial multiplication x 4 + x 3 + + 1.x + 1. x 4 + x 3 + + 1 x 5 + x 4 + +x. x 5 + + x 3 +x + 1since x 4 + x 4 = 0. Division is of particular interest when LFSRs are used for response compaction. x 2 + x + 1. x 2 + 1 ) x 4 + x 3 + + 1 x 4 + + x 2. x 3 + x 2 + + 1 x 3 + + x. x 2 + x + 1 x 2 + + 1 x the reminder R(x)=x

29. Operations on Polynomials Reminder of the division of the input sequence polynomial by the LFSR polynomial gives the signature for the compacted response Q(X) X 4 + X 3 + 1 1 1 0 0 1 X 3 + X 2 + 1 |X 7 + X 5 + X 4 + +11 1 0 1 | 1 0 1 1 0 0 0 1 X 7 + X 6 + X 4 1 1 0 1 X 6 + X 5 +11 1 0 0 0 0 1 X 6 + X 5 + +X 3 1 1 0 1 X 3 + +1 1 0 0 1 X 3 + X 2 + 1 1 1 0 1 R (X) X 2 0 1 0 0 Polynomial for the input data signature

30. Properties of Polynomials An irreducible polynomial is that polynomial which cannot be factored and it is divisible by only itself and 1. An irreducible polynomial of degree n is characterized by :  An odd number of terms including the 1 term  Divisibility into 1 + x k, where k = 2 n - 1. Any polynomial with all even exponents can be factored and hence is reducible An irreducible polynomial is primitive if the smallest positive integer k that allows the polynomial to divide evenly into 1 + x k occurs for k = 2 n - 1, where n is the degree of the polynomial.

31. Properties of Polynomials All polynomials of degree 3 are: x 3 + 1= 0 x 3 + x 2 + 1 = 0Primitive x 3 + x + 1 = 0Primitive x 3 + x 2 + x + 1= 0 But, x 3 + 1= (x + 1)( x 2 + x + 1) x 3 + x 2 + x + 1 = (x + 1)( x 2 + 1) There are several primitive polynomial of degree N. We are interested in those with fewer terms since they need less XOR gates in the LFSR. Among primitive polynomial of degree 16 are x 16 + x 5 + x 3 + x 2 + 1 and x 16 + x 4 + x 3 + x + 1.

32. Check for Primitive Polynomial Consider a 3-rd order primitive polynomial x 3 + x + 1 = 0 If this polynomial is primitive it must divide evenly into 1 + x 7 (7 = 2 3 – 1) where 3 is the degree of the polynomial. We can check that 1 + x 7= (x 3 + x + 1)(x 4 + x 2 + x + 1)

33. Test data compression To verify response of a tested circuit use test data compression Ones count compression ex 10011010 => 0(x)=4 Transition count compression ex 10011010 => c(x) =5 Parity check compression ex 10011010 => p(x) =0 Syndrome testing (normalized # of 1’s ) ex 10011010+> s(x) =4/8 Compression using Walsh spectra Cyclic code compression (LFSR)

34. Parity Compression Computes parity

35. Ones Count If we have a test of length L and the fault-free count is m, then the possibility of aliasing is [C (L, m) - 1] patterns out of total number of possible strings of length L, (2 L - 1).

36. One Count example For m = 5 and L = 8, aliasing probability will be Pa (m) =( C(8,5)-1 ) / (2^8-1) =55 /255  0.2. Not a very reliable method

37. Transition Count Computes transitions

38. Signature Analysis Uses LFSR to obtain a signature

39. LFSR as Response Analyzer Use cyclic redundancy check code (CRCC) generator (LFSR) for response compacter Treat data bits from circuit POs to be compacted as a decreasing order coefficient polynomial CRCC divides the PO polynomial by its characteristic polynomial  Leaves remainder of division in LFSR  Must initialize LFSR to seed value (usually 0) before testing After testing – compare signature in LFSR to precomputed signature of fault-free circuit

40. Signature Analysis LFSR seed is “00000”

41. Signature by Logic Simulation Input bits Initial State 1 0 1 0 1 0 X0010001111X0010001111 X1001000010X1001000010 X2000100001X2000100001 X3000010101X3000010101 X4000001010X4000001010 Signature

42. Signature by Polynomial Division Input bit stream: 0 1 0 1 0 0 0 1 0 ∙ X 0 + 1 ∙ X 1 + 0 ∙ X 2 + 1 ∙ X 3 + 0 ∙ X 4 + 0 ∙ X 5 + 0 ∙ X 6 + 1 ∙ X 7 X2X7X7X2X7X7 + 1 + X 5 X 5 + X 3 X 3 + X 2 + X + 1 X 5 + X 3 + X + 1 Char. polynomial remainder Signature: X 0 X 1 X 2 X 3 X 4 = 1 0 1 1 0 Polynomial division equivalence of data compression

43. Test generation based on a nonprimitive polynomial x 4 + x 2 +1 generates only 6 out of possible 15 states

44. Multiple-Input Signature Register (MISR) Problem with ordinary LFSR response compacter:  Too much hardware if one of these is put on each primary output (PO) Solution: MISR – compacts all outputs into one LFSR  Works because LFSR is linear – obeys superposition principle  Superimpose all responses in one LFSR – final remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial

45. Modular MISR Example X 0 (t + 1) X 1 (t + 1) X 2 (t + 1) 001001 010010 110110 = X 0 (t) X 1 (t) X 2 (t) d 0 (t) d 1 (t) d 2 (t) +

46. Space Compaction – parallel outputs M 4 PSA 1234 M 3 M 2 M M 1 M 2 M 3 M 4 SSA 12 34 M(X)= M 1 + X 1 M 2 2 M 3 3 M 4 M 1 M 2 M 3 M 4 BELLMAC LSFR

47. Test data compression BIST To reduce the number of response data a compression Based on LFSR (signature analysis) is used. Probability that 2 sequences which differ by 1 bit only will have the same signature is zero Data entering LFSR serially produces a reminder of the division of the data stream polynomial by the polynomial used for LFSR design

48. Test data compression BIST A faulty data stream will yield the same signature (reminder of polynomial division) as a fault-free data when they have the same reminder The likelihood of this is in the range of where n is the number of the compressor bits The same effect can be obtained on multi-input shift registers with faster processing speed & smaller chip area. Fault-free signature 2 n -1 faulty signatures

49. Test data compression BIST As in the single-input case the probability of detecting uniformly distributed fault in the output stream is (1 - 2 -n ) Probability of not detecting error after checking its signature is greater than 2 -n - the probability of not catching the signature error. Example 1: n = 4, Aliasing probability = 6.25% Example 2: n = 8, Aliasing probability = 0.39% Example 3: n = 16, Aliasing probability = 0.0015%

50. LFSR Design Guidelines Chose r large enough to reduce 2 -r Repeat test using different feedback connections Repeat test with different test vector Compress serial output of MISR into LFSR to capture errors In using LFSR for data compression:

51. BILBO Registers Built-in logic block observation BILBO is widely used in BIST applications BILBO which is a special purpose LFSR can be used as latches & shift register during normal mode Four modes of operation depend upon B 1 B 2 values, for B 1 B 2 equal to : 11 BILBO is a set of register cells 00 BILBO is a LFSR 10 BILBO is a multiple-input signature analysis or pseudorandom test generator 01 is a register reset mode - all registers are set to zero

52. Test Per Scan BIST Scan register Comb. logic Scan register Comb. logic Scan register Comb. logic PG RA BIST Control logic PI and PO disabled during test BIST enable Go/No-go signature

53. Built-in Logic Block Observer (BILBO) Combined functionality of D flip-flop, pattern generator, response analyzer, and scan chain  Reset all FFs to 0 by scanning in zeros

54. C1 C2 Scan-in (a) BILBO Registers

57. Mode 1 : B 1 B 2 = 11

58. Mode 2 : B 1 B 2 = 00

59. Mode 3 : B 1 B 2 = 10

60. A general BIST configuration incorporating BILBO registers

61. A BILBO configuration including all memory elements

62. Subcircuit partitioning & diagnostics minimize BIST overhead minimize the performance degradation incorporate the memory elements in BILBO registers maximize fault coverage - use exhaustive test if necessary Partitioning is useful to reduce size of UUT & increase fault coverage. Partitioning objectives:

63. Subcircuit partitioning & diagnostics Example : Partitioning of a circuit for autonomous testing

64. Subcircuit partitioning & diagnostics Example : Partitioning of a circuit for autonomous testing

65. Subcircuit partitioning & diagnostics no don’t care allowed initialize all memory elements (preferably include them in BILBO register) avoid race & hazard Partitioning requirements Some diagnostics is possible in BIST, but additional test must be run to identify faulty submodule

66. BIST Summary LFSR pattern generator and MISR response analyzer – preferred BIST methods BIST has overheads: test controller, extra circuit delay, primary input MUX, pattern generator, response compacter, DFT to initialize circuit and test the test hardware (should not take more that 5% of the design area) BIST benefits:  At-speed testing for delay and stuck-at faults  Drastic ATE cost reduction  Field test capability  Faster diagnosis during system test  Less effort to design testing process  Shorter test application times