1. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Licensed Electrical & Mechanical Engineer BMayer@ChabotCollege.edu Engineering 43 Series/Parallel, Dividers, Nodes & Meshes

2. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 2 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Series Parallel  Up To Now We Have Studied Circuits That Can Be Analyzed With One Application Of KVL Or KCL  We will see That In Some Situations It Is Advantageous To Combine Resistors To Simplify The Analysis Of A Circuit  Now We Examine Some More Complex Circuits Where We Can Simplify The Analysis Using Techniques: Combining Resistors Ohm’s Law

3. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 3 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Resistor Equivalents  Series Resistors Are In Series If They Carry Exactly The Same Current  Parallel Resistors Are In Parallel If They have Exactly the Same Potential Across Them

4. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 4 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Conductance Equivalents  ReCall: G = 1/R  For SERIES Connection  For PARALLEL Connection G S = 1.479 S G P = 15 S

5. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 5 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Combine Resistors Example: Find R AB 6k||3k = 2k (10K,2K)SERIES SERIES (4K,2K)SERIES (3K,9K)SERIES

6. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 6 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis More Examples  Step-1: Series Reduction  Step-2: Parallel Reduction 9 kΩ

7. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 7 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example w/o Redrawing  Step-2: 12k   12k = 6k  Step-3: 3k   6k = 2k  Step-1: 4k↔8k = 12k  Step-4: 6k   (4k↔2k) = 3k = R AB

8. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 8 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Series-Parallel Resistor Circuits  Combing Components Can Reduce The Complexity Of A Circuit And Render It Suitable For Analysis Using The Basic Tools Developed So Far Combining Resistors In SERIES Eliminates One NODE From The Circuit Combining Resistors In PARALLEL Eliminates One LOOP From The Circuit

9. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 9 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis S-P Circuit Analysis Strategy  Reduce Complexity Until The Circuit Becomes Simple Enough To Analyze  Use Data From Simplified Circuit To Compute Desired Variables In Original Circuit Hence Must Keep Track Of Any Relationship Between Variables

10. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 10 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example – Ladder Network  Find All I’s & V’s in Ladder Network 1 st : S-P Reduction 2 nd : S-P Reduction –Also by Ohm’s Law

11. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 11 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Ladder Network cont. Final Reduction; Find Calculation Starting Points Now “Back Substitute” Using KVL, KCL, and Ohm’s Law –e.g.; From Before

12. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 12 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The Voltage Divider  Ohm’s Law in KVL  Find i(t) by   Ohm’s Law KVL ON THIS LOOP

13. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 13 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Voltage Divider cont.  Now Sub i(t) Into Ohm’s Law to Arrive at The Voltage Divider Eqns    Quick Chk → In Turn, Set R 1, R 2 to 0 KVL ON THIS LOOP

14. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 14 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis V-Divider Summary  Governing Equations The Larger the R, The Larger the V-drop  Example Gain/Volume Control –R 1 is a Variable Resistor Called a Potentiometer, or “Pot” for Short

15. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 15 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Volume Control Example Case-I → R 1 = 90 kΩ Case-II → R 1 = 20 kΩ 30kΩ 9 V

16. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 16 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Practical Example  Power Line Also 8.25% of Pwr Generated is Lost to Line Resistance! * How to Reduce Losses?  Power Dissipated by the Line is a LOSS  Using Voltage Divider

17. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 17 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Equivalent Circuit  The Equivalent Circuit Concept Can Simplify The Analysis Of Circuits For Example, Consider A Simple Voltage Divider SERIES Resistors → 1 R 2 R  21 RR  –As Far As The Current Is Concerned Both Circuits Are Equivalent  The One On The Right Has Only One Resistor

18. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 18 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Schematic vs. Physical  Sometimes, For Practical Construction Reasons, Components That Are Electrically Connected May Be Physically Quite Apart Each Resistor Pair Below Has the SAME Node-to-Node Series-Equivalent Circuit

19. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 19 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis COMPONENT SIDE CONNECTOR SIDE ILLUSTRATING THE DIFFERENCE BETWEEN PHYSICAL LAYOUT AND ELECTRICAL CONNECTIONS PHYSICAL NODE SECTION OF 14.4 KB VOICE/DATA MODEM CORRESPONDING POINTS

20. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 20 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Generalization  Multiple v-Sources  Voltage Sources In Series Can Be Algebraically Added To Form An Equivalent Source We Select The Reference Direction To Move Along The Path i(t) –Voltage Rises Are Subtracted From Drops  Apply KVL

21. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 21 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Multiple v-Source Equivalent  Collect All SOURCES On One Side  The Equivalent Circuit: V-source in Series ADD directly

22. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 22 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Generalization  Mult. Resistors  Apply KVL (rise = Σdrops)  Now by Ohm’s Law  And Define R S  Then Voltage Division For Multiple Resistors KVL [R k /R S ] is the Divider RATIO

23. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 23 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example  Find: I, V bd, P 30kΩ  Apply KVL & Ohm  Solving for I  Now V bd  Finally, The 30 kΩ Resistor Power Dissipation APPLY KVL TO THIS LOOP

24. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 24 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Examples  Find: I, V bd Use KVL and Ohm’s Law APPLY KVL TO THIS LOOP  Find V S by V-Divider The V 20k Divider Eqn Solving for V S

25. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 25 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis When In Doubt → ReDraw  From The Last Diagram It Was Not Immediately Obvious That This Was a V-Divider Situation UnTangle/Redraw at Right

26. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 26 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Single Node-Pair (SNP) Circuits  SNP Circuits Are Characterized By ALL the Elements Having The SAME VOLTAGE Across Them → They Are In PARALLEL  SNP Example This Element is INACTIVE The Inactive Element Has NO Potential Across it → SHORT Circuited

27. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 27 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis UnTangling Reminder  Nodes Can Take STRANGE Shapes Low Distortion Power Amplifier NODE → A region of Constant Electrical Potential e.g.; a group of connected WIRES is ONE Node

28. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 28 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis LOW VOLTAGE POWER SUPPLY FOR CRT - PARTIAL VIEW SOME PHYSICAL NODES COMPONENT SIDECONNECTION SIDE

29. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 29 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The Current Divider  Basic Circuit  The Current i(t) Enters The Top Node then Splits, or DIVIDES, into the the Currents i 1 (t) and i 2 (t)  Apply KCL at Top Node  Use Ohm’s Law to Replace Currents APPLY KCL

30. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 30 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The Current Divider cont.  Basic Circuit  By KCL & Ohm  The Current Division  Define PARALLEL Resistance

31. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 31 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Current Divider Example  By I-Divider  For This Ckt Find: I 1, I 2, V o  When in doubt… REDRAW the circuit to Better Visualize the Connections 2-Legged Divider is more Evident

32. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 32 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Real World Example  Car Stereo and Circuit Model  Use I-Divider to Find Current thru the 4Ω Speakers  Thus the Speaker Power  Power Per Speaker by Joule

33. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 33 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Current & Power Example  Find I 2 by I-Divider OR KCL Choose KCL  For This Ckt Find: I 1, I 2, P 40k  Power ABSORBED by 40 kΩ Resistor  By I-Divider KCL  The 40k Power by RI 2

34. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 34 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Generalization: Multi i-Sources  KCL on Top Node:  Given Single Node-Pair Ckt w/ Multiple Srcs  The Equivalent Ckt  Combine Src Terms To Form Equivalent Source KCL

35. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 35 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Generalization: Multi i-Sources  By Analysis and Electrical Physics of KCL   Thus CURRENT Sources in PARALLEL ADD directly Compare to VOLTAGE Sources in SERIES which also ADD Directly =

36. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 36 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis i-Source Example  Combine Srcs to Yield Equivalent Ckt  For This Ckt Find V o, and the Power Supplied by the I-Srcs  V o by Ohm’s Law mA 10 mA 15  k 3  k 6   O V  Use PASSIVE SIGN Convention for Power

37. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 37 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Generalization: Multi Resistors  KCL on Top Node:  Given Single Node-Pair Ckt w/ Multiple R’s Ohm’s Law at Each Resistor  The Equivalent Resistance & v(t) KCL

38. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 38 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Multi-R Example  Find R p  For This Ckt Find i 1, and the Power Supplied by the I-Source  Recall the General Current Divider Eqn mA 8 k 4 k 20 k 5 1 i

39. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 39 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Multi-R Example cont.  Find v for Single- Node-Pair by Ohm  Find i 1, by Divider Take Care with Passive Sign Conv mA 8 k 4 k 20 k 5 1 i Note: this time For Passive Sign Convention CURRENT Direction assigned as POSITIVE  Find P src by vi

40. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 40 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Multi-R: Alternative Approach  The Ckt After the R-Combination  Start by Combining R’s NOT associated with i 1  Now Have 1:1 Current Divider so mA 8 k 4 k 20 k 5 1 i 20k||5k mA 8 k 4 k 4 1 i

41. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 41 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example: Multi-R, Multi-I src SNP  Soln Game Plan: Convert The Problem Into A Basic CURRENT DIVIDER By Combining Sources And Resistors  Given Single Node-Pair Ckt: Find I L  Combine Sources Assume DOWN = POSITIVE

42. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 42 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Multi-R, Multi-I src SNP cont.  Next Combine Parallel Resistors  Given Single Node-Pair Ckt: Find I L  I L by 3:1 I-Divider  Then the Equivalent Circuit → Note MINUS Sign

43. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 43 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The SAME Ckt Can Look Quite Different 9mA I1 I2 I1 I2 I1 I2

44. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 44 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis UnTangling Utility  Redrawing A Circuit May, Sometimes, Help To Better Visualize The Electrical Connections I1 I2 Be FAITHFUL to the Node-Connections I1I2

45. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 45 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Another Example  Alternatives for P By vi & passive sign:  For This Ckt Find the I-Src Power, P 20  Use ||-Resistance k 2 k 4 k 3 mA 20 +V_+V_ By Joule and Energy Balance

46. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 46 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Nodal Analysis (based on KCL)  A Systematic Technique To Determine Every Voltage and Current in a Circuit  The variables used to describe the circuit will be “Node Voltages” The voltages of each node Will Be Determined With Respect To a Pre-selected REFERENCE Node –The Reference Node is Often Referred to as  Ground (GND)  Or  COMMON

47. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 47 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Consider Resistor Ladder  Goal: Determine All Currents & Potentials in this “Ladder” Network  Plan Use Series/Parallel Transformation to Find I 1 Back-Substitute Using KVL, KCL, Ohm to Find Rest

48. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 48 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Series-Parallel Transformations  Xform1 Combine 3 Resistors at End of Network  Xform2 Combine 3 Resistors at End of Network  Note By Ohm’s Law

49. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 49 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Xform cont.  Xform3 To Single-Loop Ckt  Now Back Substitute Recall By KCL

50. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 50 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Xform cont.  Recall Xform2  In Summary I 1 = 1 mA I 2 = I 3 = 0.5 mA I 4 = 0.375 mA I 5 =0.125 mA V a = 3 V V b = 1.5 V V c = 0.375 V  Finally by KCL

51. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 51 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Node Analysis Perspective KVL REFERENCE   In General: V x5 = V x − V 5 = V x − 0 = V x Then the KVL Eqns  Take Node-5 As the Ref, →V 5 = 0, Always

52. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 52 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Node Analysis cont  If We Know V a, V b, and V c, Then Can Calc V 1, V 2, V 3 by KVL, Then –Use Ohm’s Law to Find I 1 →I 5  i.e., If we Know All Node Potentials, Then Can Calc All Branch Currents Theorem: IF ALL NODE VOLTAGES WITH RESPECT TO A COMMON REFERENCE NODE ARE KNOWN, THEN ONE CAN DETERMINE ANY OTHER ELECTRICAL VARIABLE FOR THE CIRCUIT

53. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 53 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis ALWAYS Define Reference Node  The Statement V 1 = 4V is Meaningless UNTIL The Designation of a REFERENCE NODE  By Convention The Ground (GND) Symbol Indicates the Reference Point ALL Node Voltages are Measured Relative to GND

54. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 54 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Strategy for Node Analysis 1.Identify All Nodes And Select A Ref. Node 2.Identify Known Node Voltages 3.at Each Node With Unknown Voltage Write A KCL Equation e.g.,  (Sum Of Current Leaving) =0 4.Replace Currents in Terms Of Node V’s  Yields Algebraic Eqns In The Node Voltages Final Desired Eqn Set REFERENCE

55. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 55 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Node Equation Mechanics  When Writing Node Equations At Each Node We Can Choose Arbitrary Directions for Currents Then select any form of KCL  When The Currents Are Replaced In Terms Of The Node Voltages The Node Eqns That Result Are The Same Or Equiv.

56. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 56 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Node Eqn Mechanics cont.  When Writing The Node Equations Use Ohm’s Law to Write The Equation Directly In Terms Of The Node Voltages BY Default Use KCL In The Form Sum-of- currents-leaving = 0 –But The Reference Direction For The Currents Does NOT Affect The Node Equation

57. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 57 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Ckts w/ Independent Sources  At Node-1 Using Resistances  Using Conductances Eliminates Tedious Division Operations  Replacing R’s w/ G’s At Node-1 At Node-2

58. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 58 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Node Analysis of Indep Src Ckts  ReOrder Terms in Eqns for i A & i B  The Manipulation Of Systems Of Algebraic Equations Can Be Efficiently Done Using Matrix Analysis c.f., MTH-6 or ENGR-25 (MATLAB)  The Model For The Circuit is a System Of Algebraic Equations

59. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 59 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example  Write the KCL Eqns @ Node-1 We Visualize The Currents Leaving And Write the KCL Eqn  Similarly at Node-2 Could Use  (i Entering Node) Just as well

60. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 60 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis KCL Eqn Example  Write KCL At Each Node In Terms Of Node Voltages 3 Nodes Implies 2 KCL Equations Mark the nodes (to insure that None is missing) Select C as Reference  Solving by Algebra, Find:  Two simple eqns in Two Unknowns

61. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 61 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Linear Algebra Analysis  Recall R=1/G, Then Insert Numerical Values, and Change to Time Independent Notation (All CAPS)  The Math Model  The Node Eqns in Conductance Form

62. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 62 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Linear Algebra Analysis cont.  The Numerical Model  Multiply the 1 st Eqn by 4kΩ to Find V 1 in Terms of V 2  Back Sub into 2 nd eqn  Then V 2  And V 1  Alternatively, Multiply Both Sides of Math Model by LCD in kΩ R.H.S. of Eqn Now in Volts V 1, V 2 CoEffs are No.s

63. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 63 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Linear Algebra Analysis cont.  The “Clean” Eqns  Proceed with Gaussian Elimination Add Eqns to Eliminate V 2 Back Substitute to Find V 2

64. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 64 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Use Matrix Algebra  Recall The Math Model  From MTH-6 the Form of Matrix Multiplication In this Case  The Matrix Eqn Soln In this Case  Calculating the Matrix Inverse, G -1, is NOT Trivial Use Matrix Manipulation –Adjoint Matrix –Determinant Calculation Or use MATLAB

65. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 65 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis GV = I  By MATLAB  Construct the Coefficient Matrix G >> G = [1/4e3 -1/6e3; -1/6e3 1/3e3] G = 1.0e-003 * 0.2500 -0.1667 -0.1667 0.3333  Construct the Constraint Vector, I >> I = [1e-3; -4e-3] I = 0.0010 -0.0040  Matrix Inversion by “Left” Division for V >> V = G\I V = -6 -15

66. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 66 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example Ckt w/ V-controlled I src  Write Node Equations  Treat Dependent Source as a Normal Current-Source Node Eqns  Express Controlling Variable In Terms Of Node Voltages

67. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 67 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example Ckt w/ V-controlled I src  4 Eqns in 4 Unknowns Solve Using Most Convenient Method –Choose SUB & GAUSSIAN ELIM  Sub for v x in v x I src  Continue w/ Gaussian Elim OR Use Matrix Algebra

68. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 68 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Solve Using MATLAB  Define Components (m-file Node_Anal_0602.m) R1 = 1000; R2 = 2000; R3 = 2000; R4 = 4000; %resistances in Ohms iA = 0.002; iB = 0.004; %sources in Amps Alpha = 2; %gain of dependent source in Siemens

69. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 69 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Solve Using MATLAB cont  Define Coefficient Matrix G=[(1/R1+1/R2), -1/R1, 0; % first Matrix row -1/R1,(1/R1+alpha+1/R2),-(alpha+1/R2); % 2nd row 0, -1/R2,(1/R2+1/R4)] %third row. G = 0.0015 -0.0010 0 -0.0010 2.0015 -2.0005 0 -0.0005 0.0008

70. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 70 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Solve Using MATLAB cont  Define Constraint Vector I=[iA;-iA;iB];  Solve by Left/Back Division; V in volts V=G\I % end with carriage return and get the ReadBack V = 11.9940 15.9910 15.9940

71. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 71 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Loop Analysis (Based on KVL)  Loop Analysis is The 2 nd Systematic Technique To Determine All Currents And Voltages In A Circuit IT Is the DUAL To Node Analysis –It First Determines All Currents In A Circuit And Then It Uses Ohm’s Law To Compute Voltages There Are Situations Where Node Analysis Is Not An Efficient Technique And Where The Number Of Equations Required By Loop Analysis Is Significantly Smaller

72. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 72 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Loop Analysis Illustration  Apply Node Analysis  Observe  Need 3 Eqns to Find All Node Potentials; 2  4  Notice There is Only ONE Current Flowing Thru All Components A Single Loop Ckt Can Use Ohm’s Law to Determine Voltages  Apply KVL for Clockwise Loop Starting at GND I GND Have 4 Non-Ref Nodes One SuperNode One Node Connected to GND Thru a V-src

73. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 73 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Loop Analysis Illustration cont  Now Use Ohm’s Law to Express V’s In Terms of the Loop Current  By KVL  Note: Recalling that V=IR Allows Writing the Ohm Eqn “by Inspection” for a Single Loop Ckt  The Loop Generates a SINGLE Eqn to Yield the Loop CURRENT GND KVL

74. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 74 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Loops, Meshes, Loop-Currents  Each Component Is Characterized By The VOLTAGE ACROSS It CURRENT THRU It  A Loop Is A Closed Path That Does Not Go Twice Over Any Node  This Circuit Has 3 Loops 1.fabef 2.ebcde 3.fabcdef

75. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 75 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Loops, Meshes cont.  A MESH is a LOOP That Does Not Enclose Any OTHER Loop This Ckt Has Meshes –fabef  A Loop Current is a Fictitious or Virtual Current That is Assumed to Flow Around a Loop The Loop Currents of This Ckt –I 1, I 2, I 3  Mesh Current = Current Within a Mesh Loop e.g.: I 1, I 2 –ebcde

76. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 76 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Loops, Meshes cont.  Claim In a Circuit, the Current Through Any Component Can Be Expressed In Terms of the (perhaps multiple) Loop Currents  Ckt Examples The DIRECTION Of The Loop Currents is SIGNIFICANT FACT –Not ALL Loop Currents are Required To Compute All The Currents Through Components

77. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 77 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Loops, Meshes cont.  For Every Circuit There is a MINIMUM Number of Loop Currents Needed to Find Every Current in the System Such A Collection is Called the “MINIMAL SET” (of Loop Currents)  For a Given Circuit Let B  Number of BRANCHES N  Number of NODES  The Minimum Number of Loop Currents is

78. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 78 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Illustration  For This Ckt B = 7 N = 6 L = 7-(6-1) = 2  Need Two Loop Currents The Currents Shown are MESH Currents –Hence They are Independent and form a Minimal Set  Determination of Loop Currents KVL on Left Mesh KVL on Right Mesh Using Ohm’s Law

79. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 79 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Illustration cont.  Substituting and Rearranging  We Obtain in MATRIX FORM the Loop Equations for This Circuit

80. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 80 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Mesh Practice  Write The Mesh Equations  Some Bookkeeping 8 BRANCHES 7 NODES L = 8-(7-1) = 2 –Need TWO Mesh Currents  This is MESH Current Practice Choose as the Two Loops Meshes –i1–i1 –i2–i2  Identify All Voltage Drops  KVL on Bottom Mesh  KVL on Top Mesh

81. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 81 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Mesh Practice cont.  Now Use Ohm’s Law To Find The Mesh Current Equation Set

82. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 82 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Develop a ShortCut  Whenever An Element Has More Than One Loop Current Flowing Through It We Calculate NET Current In The DIRECTION of TRAVEL  Draw The Mesh Currents Orientation can be arbitrary, But Conventionally Defined as CLOCKWISE  NOW Write KVL For Each Mesh Apply Ohm’s Law To Every Resistor

83. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 83 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Develop a ShortCut cont  At Each Loop must Follow The Passive Sign Convention Using Loop Current REFERENCE DIRECTION This Defines the Polarity of the Voltage Drops  Then KVL for Meshes 1 & 2  Note The NET Currents

84. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 84 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numerical Example  Use Loop Analysis to Find I o  SHORTCUT: POLARITIES ARE NOT NEEDED. Apply Ohm’s Law To Each Element As KVL Is being written  KVL for Meshes 1 & 2  Collect Like Terms & Solve

85. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 85 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numerical Example - Alternate  Alternative Loop Current Selection  KVL for Mesh1 & Loop2  Collect Like Terms & Solve  In This Case one mesh and one loop I o = I 1 –This Selection is More Efficient than 2 small meshes; Only Need to Find l 1

86. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 86 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Circuits w/ Indep. I-Sources  Find Both V o & V 1  There is NO Relationship Between V 1 and the 2 mA Source Current However... The Mesh-1 Current is CONSTRAINED by the 2mA Source –Thus the Mesh-1 Eqn  In General Current Sources That Are NOT SHARED By Other Meshes (Or Loops) Serve To DEFINE a Mesh (Loop) Current And Reduce The Number Of Required Equations

87. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 87 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Circuits w/ Indep. I-Sources cont  The Mesh-2 KVL Eqn  Then  ReArranging Find Equivalent Eqn  To Obtain V 1 Apply KVL To Any Closed Path That Includes V 1  Use I 1 Constraint to Calculate I 2 KVL

88. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 88 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numerical Example  Two Mesh Currents Are Defined By Current Sources  Only Need Eqn for Mesh-3

89. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 89 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numerical Example cont  Collect Terms for eqn-3  Finally Use KVL to Calculate V o  Then I 3 KVL FOR Vo

90. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 90 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis STOP Here if Short on Time

91. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 91 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Eqns by “Inspection”  If The Circuit Contains Only INDEPENDENT VOLTAGE Sources Then The Mesh Equations Can Be Written “By Inspection” MUST HAVE All Mesh Currents With The Same Orientation  In loop “k” The Coefficient Of I k Is The Sum Of Resistances Around The Loop  The Right Hand Side Is The Algebraic Sum Of Voltage Sources Around The Loop VoltageRise = POSITIVE on R.H.S. of eqn

92. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 92 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Eqns by “Inspection” cont  The Coefficient Of I j Is The Sum Of Resistances COMMON To Both k and j and With a NEGATIVE Sign  In This Example Loop1: k = 1, j = 2 Loop2: k = 2, j = 1

93. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 93 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Equation Practice  Loop-1 Coefficient of I 1  Similarly The Coeffs for Loop-2 Coefficient of I 2 Coefficient of I 3 Right Hand Side (RHS)  In Summary for Loop1

94. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 94 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Equation Practice cont.  In Summary for Loop-2  Applying the Method to Loop-3 Yields  Solve 3-Eqns in 3-Unknowns Using Normal Linear Algebra, or MATLAB, Techniques

95. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 95 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numerical Example  Use Mesh Eqns to Determine V o 1.Draw the Mesh Currents 2.Write the Mesh Eqns for Mesh-1 & Mesh-2  Divide Both Sides of Both Eqns by 1kΩ Units on RHS become V/kΩ, or mA  Solve System of Eqns

96. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 96 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example 1.Draw the Mesh Currents 2.Write Mesh Eqns by KVL  Or Eqns by Inspection  Calculate Currents Using Multi-Eqn Solver Tools 4 Eqns in 4 unknowns –Solve using Standard Linear Algebra Techniques –Perfect for MATLAB

97. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 97 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis All Done for Today A Different Type of NODE BRANCHES Connect to NODES

98. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 98 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis WhiteBoard Work LLet’s Use KCL to Derive the R eq for N Parallel Resistors Done Previously

99. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 99 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Licensed Electrical & Mechanical Engineer BMayer@ChabotCollege.edu Engineering 43 Appendix Δ↔WYE & others

100. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 100 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Recall Passive Sign Convention  If V’ Drops R←L i’ by Passive Sign Convention  If V Drops L→R i by Passive Sign Convention

101. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 101 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Single Loop Ckts - Background  Using KVL And KCL We Can Write Enough Equations To Analyze ANY Linear Circuit  Begin The Study Of Systematic And Efficient Ways Of Using The Fundamental KCL & KVL Circuit Laws This Time → Single LOOP Circuits

102. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 102 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The Power of Loop Analysis  Consider this Circuit  Alternative Analyses Write N-1 (5) KCL Equations Determine Only the SINGLE Loop Current –An Easy Choice  The Plan for Loop Analysis Begin With The Simplest One-Loop Circuit Extend Results To Multiple-Source and Multiple-Resistor Circuits

103. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 103 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis “Inverse” Voltage Divider  The Std V-Divider 1 R + - 2 R S V   O V Inverse Divider Use Inverse Divider  Example Find V S

104. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 104 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example  Find V x, V ab P 3Vx –The Power Absorbed or Supplied By the Dependent Source  Apply KVL + - x V 3  V 4 k 4   X V a b S V VV S 12  + - 1 2 3 1 2 3  Find DS Power Passive Sign Conven.  Ohm’s Law Then Pwr ABSORBED

105. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 105 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example  Find: V DA, V CD, I Apply KVL & Ohm k 30 + - + - V 9 k 20 k 10 A B C D E 1 2 1 2 12V Ohm’s Law

106. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 106 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis WhiteBoard Work  Let’s Work This Problem

107. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 107 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Inverse Series Parallel Combo  Find R: Simple Case Constraints –V R = 600 mV –I = 3A –Only 0.1Ω R’s Available  Recall R = V/I Since R>R avail, Then Need to Run in Series

108. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 108 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis More Complex Case  Find R for Constraints V R = 600 mV I = 9A Only 0.1Ω Resistors Available 0.1║(0.1↔0.1) EEither of These 0.1Ω R-Networks Will Work 33.33 mΩ

109. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 109 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Effect Of Resistor Tolerance  The R Spec: 2.7k, ±10%  What Are the Ranges for Current & Power? I = V/R P = V 2 /R For Both I & P the Tolerance.: -9.1%, +11.1% –Asymmetry Due to Inverse Dependence on R

110. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 110 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Final Example  Find V S Straight-Forward VBVB IBIB ISIS Or, Recognize As Inverse V-Divider

111. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 111 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Final Example cont  Inverse Divider Calculation VBVB IBIB ISIS

112. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 112 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Wye↔  Transformations  This Circuit Has No Series or Parallel Resistors  If We Could Make The Change Below Would Have Series- Parallel Case

113. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 113 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Y↔  Xforms cont  Then the Circuit Would Appear as Below and We Could Apply the Previous Techniques

114. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 114 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Wye↔  Transform Eqns   →Y (pg. 58)  →Y  ←Y R ac =R 1 ||(R 2 ↔R 3 ) R ab = R a + R b   ←Y (pg. 58)

115. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 115 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis  ↔Y Application Example  Find I S  Connection  Calc I S R eq Use the  →Y Eqns to Arrive at The Reduced Diagram Below

116. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 116 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Another  ↔Y Example  For this Ckt Find V o Convert this Y to Delta Keep This Node-Pair

117. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 117 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Another  ↔Y Example cont  Notice for Y→Δ in this Case Ra = Rb = Rc = 12 kΩ Only need to Calc ONE Conversion  The Xformed Ckt ||-R’s Form a Current Divider

118. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 118 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Another  ↔Y Example cont  The Ckt After ||-Reductions  Can Easily Calc the Current That Produces Vo  Then Finally V o by Ohm’s Law

119. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 119 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis “BackSubbing” Example  Given I 4 = 0.5 mA, Find V O

120. BMayer@ChabotCollege.edu ENGR-43_Lec-02a_SP_VI-Divide_NodeMesh.pptx 120 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis BackSubbing Strategy  Always ask: What More Can I Calculate? In the Previous Example Using Ohm’s Law, KVL, KCL, S-P Combinations - Calc: