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Graphics Hardware and Software Architectures
High End Computing Graphics Hardware and Software Architectures
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Presentation Overview
Short History Today High End Computer Architecture Specialized Graphics Hardware Software Architecture Instantiated
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Short History Federally sponsored University research began in 1965
Ivan Sutherland and Jim Clark New technologies make graphics accessible VLSI chips High Level Programming Languages Less expensive HW led to growing market Jim Clark developed Geometry Engine Founded SGI (Silicon Graphics Inc.) VLSI- very large scale integrated chips GE developed late 70’s early 80’s
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Today SGI is an industry leader
High Performance Graphics Computer Development Our Example: Onyx2 InfiniteReality2 Designed to provide system support for OpenGL
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High End Computer Architecture Onyx2 InfiniteReality2
ccNUMA (Cache Coherent Non Uniform Memory Access) Architecture Automatic scaling of system and graphics bandwidth Low transport latency Continuous, real-time fly-overs of large terrain Support interactive, immersive visualization of unbounded volumes (Visible Human)
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Onyx2 InfiniteReality2 cont.
Midplane XIO XIO Mid- plane Node Router XIO Mid- plane Node Router XIO Node Node Node XIO Router Mid- plane Router Router Interconnection fabric Node Router XIO Router Router Node Node XIO XIO Midplane ccNUMA Diagram
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Onyx2 InfiniteReality2 cont.
RAM R10000 HUB DMEM R10000 I/O Cards C R O S B W PCI Graphics I/O MIDPLANE Mid- plane Node Router XIO Graphics
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Graphics Hardware C R O S B Graphics Pipeline W MIDPLANE
I/O Cards C R O S B W PCI Graphics I/O MIDPLANE Display Generator Raster Manager Geometry Board Graphics Pipeline
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Graphics Pipeline Supports primitives Primitives combine Polygons
Vectors Points Parametric polynomial surfaces Primitives combine Mesh polygon strips with common vertices
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Host Interface Processor
Geometry Board Geometry Processor Transformations Lighting Clipping Projection Data Management Pixels Textures Video GE16 Crossbow Host Interface Processor Geometry Distributor Geometry Engine (GE16) Geometry – Raster FIFO Geometry Board
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Raster Manager RM9 Raster Manager Frame buffer Texture Fragment Memory
Generator Pixels Texels Processing 80 Image Engines Frame buffer RM9 Vertex Bus Raster Manager Raster Memory (RM9)
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Display Generator De-interleaver Display Channel DAC ENC
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Cosmic Head
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Software Architecture OpenGL
Multi-platform industry standard graphics library A state machine Native graphics programming interface for Onyx2 InfiniteReality2 Implemented within graphics subsystem Need software to take advantage of the great graphics hardware
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Command Tokens to Display Lists
HIP Geometry Distributor GE16 FIFO Fragment Operations Feedback selection Geometry Data Command Tokens to Display Lists Pixel Data Unpack Vertices Unpack / Pack Pixels Vertex Bus Texture Memory Fragment Generator Image Engines Frame buffer RM9 Texture Memory Operations Point, Line, Polygon Rasterization Image Rasterization Frame buffer Vertex Operations Pixel Operations De-interleaver Display Channel ENC DAC
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Software Architecture Mapped Over Hardware Architecture
Feedback Selection Geometry Command Tokens Pixels Unpack Vertices Display Lists Unpack/ Pack Vertex Operations Pixel Point, Line, And Polygon Rasterization Texture Memory Image Fragment FB Geom. Dist. Frag. Gen. Fragment Processing HIP GE16 TMEM Frame buffer
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Some Specifications of Onyx2 Infinite Reality2
Two or four 4MB cache MIPS R10000 processors 128MB to 8GB of memory Single graphics pipeline with one or two Raster Managers 64MB of texture memory Up to 160MB of frame buffer capacity
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Mips R10000 This processor features a four-way superscalar RISC processor that fetches and decodes four instructions per cycle, speculatively executes beyond branches, with a four-entry branch stack, uses dynamic out-of-order execution, implements register renaming using map tables, and achieves in-order graduation for precise exceptions.
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