1. CALIBRATION BOARDS FOR THE LAr CALORIMETERS ATLAS N. Dumont-Dayot, M. Moynot, P. Perrodo, G. Perrot, I. Wingerter-Seez Laboratoire d’Annecy-Le-Vieux de Physique des Particules IN2P3-CNRS 74941 Annecy-Le-Vieux, France C. de La Taille, J.P. Richer, N. Seguin-Moreau, L. Serin Laboratoire de l’Accélérateur Linéaire, Université Paris-Sud – B.P. 34 91898 Orsay Cédex, France K. Jakobs, U. Schaefer, D. Schroff Institut für Physik Universität Mainz Mainz, Germany

2. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 2 OUTLINE ATLAS LAr CALORIMETER READOUT REQUIREMENTS HISTORY ANALOG and DIGITAL DMILL CHIPS 8 CHANNELS BOARD 128 CHANNELS BOARD

3. Calibration : 116 boards @ 128 ch Front End Board (FEB) : 1524 boards @ 128 ch ATLAS Lar EM calorimeter readout Electrodes Cryostat Cold to warm Feedthrough Readout and Calib. signals Front End Crate: CALIB.FEBTBBController

4. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 4 CALIBRATION: Requirements and Principle Goal: Inject a precise current pulse [Ical] as close as possible as the detector pulse Rise time < 1ns. Decay Time around 450 ns. Dynamic range : 16 bits (100 μV to 5V). Integral non linearity < 0.1%. Uniformity between channels better than 0.25% (to keep calorimeter constant term below 0.7%) Timing between physics and calibration pulse ±1ns Operation in around 100 Gauss field Radiation hardness: 50 Gy, 1.6 10 12 Neutrons/cm 2 in 10 years Taking account safety factors, DMILL chips must be qualified up to 500 Gy, 1.6 10 13 Neutrons/cm 2 Run at a few kHz LAr PULSER 0.1% Rinj ROOM T HF SWITCH

5. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 5 HISTORY 12 boards produced in 1998 with COTS [LEB98 and LEB99] 5 years successful operation in beam tests. Problems were mainly chips badly soldered and dead transistors, but Radiation tolerance: Inadequate with COTs that failed irradiation tests at 20 Gy Chips migration to DMILL technology Improve parasitic signal at DAC=0: About 1.2 GeV equivalent (3 % of the high gain range) HF switch redesigned with a PMOS transistor instead of 4 PNPs transistors in parallel: 10 times improvement Delay chip linearity and monotony marginal (and strongly dependent on power supply) DAC time stability improvement Digital part: to be simplified, 10 ALTERAs removed and replaced by DMILL ASICs.

6. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 6 128 CHANNELS CALIBRATION BOARD : ANALOG PART A low offset op. amp. distributes the DAC voltage to the 128 channels. One low offset op.amp. per channel generates the calibration current through a 5  [0.1%]. 128 channels calibration board 16 bits DAC V follower Idc: 2uA to 200 mA HF Switch V to I conversion 5  Vout: 50 μV to 5V in 25  Low Off Op Amp

7. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 7 16 bits dynamic range (16 μV-1V), accuracy 0.1% Good stability at small DAC value External R/2R ladder and highly degenerated current sources DAC DMILL: V1 and V2 (Different Iref) Bandgap reference voltage (1.5 V) or external voltage DAC V2: Submitted in Sept 01, area : 8 mm 2 123 received in May 02, yield : 90% 16 bits DMILL DAC: requirements and design Iref External 0.1% degener. R 16 I sources DAC V2 V to I convertor External 0.1% R Bandgap DAC V2

8. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 8 DAC performance : Linearity DC measurement performed with precise multimeter Measurement performed with the Bandgap reference Accuracy: 0.01 % or 10 μV INL < 0.01%: explained by single bit linearity 0.01%

9. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 9 DAC performance Irradiation results: shown at LEB7 (Stockholm) Temperature stability (with the bandgap reference) measured on 1 DAC V2: better than -0.01%/K Due to R and Isources temperature sensitivity Time stability measured DACs V1 Temperature2547 - 51 μ V/K Vdac with all the bits ON (DAC V2) 0.02% Bit15 ON Bit0 ON 15 h

10. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 10 DMILL LOW OFFSET Op Amp: Requirements 16  V Offset around 16  V [DAC LSB] or less. Offset stable in time  10°C Temperature sensitivity : 0.1% or 1 LSB for  10°C Integral non linearity < 0.1%.  s Speed not crucial: Settling time < 100  s Input range: from 5 V to 4 V Output range: DC current 2  A 200mA DC current from 2  A to 200mA Pulse Out: 50  V to 5V in Zout=25  Pulse Out: 50  V to 5V in Zout=25  Power supplies: Op Amp: V DD = +7V V ss = +2V Op Amp: V DD = +7V and V ss = +2V. DAC V follower V to I conversion HF Switch

11. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 11 Low offset op amp design Used in 0.2% accuracy DC current source (2 μA-200 mA) (Orsay) Centroid bipolar diff. Pair 10/1.2 External 165k  0.1% collector resistors Second stage : 1000/1.2 cascoded diff. pair Fuses for fine offset trimming to ± 10 μV Output PMOS : 20,000/0.8 for I DAC =200mA DAC in Current out 5  0.1% Enable input External compens. 1 nF to V P6 External R: Window of trimming

12. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 12 Low offset op amp versions First version in 0.8 μm BICMOS AMS technology in 2000 Selection inside ±200 μV => 23/24 Op amps=95 % First DMILL chip: Op Amp V1 Op Amp design: minor modifications compared to the AMS version 40 chips received in Feb 01. Area = 1.82 mm 2 Ceramic package JLCC28 3 not working Selection inside ±200 μV => 32/37 Op amps=86 % Final version V2 Include HF switch (cost reduction) Op amp: identical as V1 Chip submitted in May 01. Area : 3 mm 2 Plastic package PQFP44 1960*1460 Layout of Op. Amp. V2 Layout of Op Amp V1

13. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 13 Op Amp performance: Offset Yield : 593 chips received Nov 01. 574 Fully functional, 19 out of working → Yield : 96% Selection inside ±200 μV : 364 Op Amp → sorting yield : 63.4% Example of offset trimming: Op Amp trimmed down to –7 μV Initial Offset:–254 μV

14. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 14 Op Amp performance Irradiation tests : Performed on V1 and shown at LEB7 (Stockholm) DC Linearity: DC output current measured with a precise multimeter. Offset not sensitive to the DAC value Residuals in µV

15. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 15 Offset stability: Time stability (10 Op Amps) Output DC current monitored  V Stability better than 10  V Temperature stability (10 Op Amps)  V/degree) for OA with the largest initial offset Largest variation (<2  V/degree) for OA with the largest initial offset  V  V over this period. 10 chips previously trimmed down to a few  V kept at 87 degree during 4 days. Stability found better than 2  V over this period.  5 or 25  V  V 40  V 90 minutes 25 °50 ° Offset variation

16. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 16 OP AMP PRODUCTION AND TEST 28000 op amps produced before the end of 2002 Use of the Grenoble robot to test them and trim op amps with offset < ± 200 µV DC measurements for 3 DAC values: Total Offset (in+-in-)  V Rc (2 nd stage offset) IDC out after PMOS Switch Check 7.5 V Power Consumption

17. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 17 DIGITAL PART CALOGIC (LAPP Annecy): Generate calib. Window and reset signals 16 Pulsers 16 Pulsers 16 Pulsers 16 Pulsers 16 Pulsers. 16 Pulsers 16 Pulsers 16 Pulsers DAC REG REG0REG1 Delay0Delay1 REG2REG3 TTC decode TTCrx SPAC I2C 4 4 32 Clock40 I2C 16 bits DAC 16 CALOGIC Reg0-3: 32 bits R/W register To enable the 128 ch. DELAY (CERN): 0-24 ns, step 1ns CALOGIC: 16 bits R/W reg. To load the DAC value TTCRx: ATLAS TTC commands SPAC: I2C frame ANALOG PART

18. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 18 Digital chips: CALOGIC Control logic : DMILL (ANNECY) Common DMILL chip to control DAC, pattern and delays registers and to decode TTCRx commands. 16 mm 2 chip, received 39 (MPW 05/01). Yield : 100% Irradiation tests SEE test performed in Feb 02 (Louvain) no SEU up to ~8 10 12 p + (60 MeV) In ATLAS < 2 SEU/yr I2C PowerOn Reset Patternregister(32 bits) Calib counter (11 bits) Resetregister Pattern CalibIn Clock40Des1 Command CalibOutAutozero TTCrxdecoding ResetOut ResetIn SCL SDA Function Select

19. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 19 Digital chips: DELAY Delay chip : DMILL (CERN) To align physics signal and calibration pulse 4 delay lines/chip 0-24 ns, 1ns step Linearity residuals: ±60 ps Jitter = 25 ps SEE test performed in Feb 02 (Louvain) 4 chips monitored One error occurred, cleared by power reset + 60 ps - 60 ps Jitter 22 ps Residuals (ns)

20. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 20 8 channels prototype towards the 128 channels board Board very different from Module 0 Channels no longer aligned but staggered in depth Difficult tuning Ground bounce 2V change with enabled channels 80 µV DAC offset DAC change with all channels on Overshoot Signal uniformity DC uniformity Damaged chips Oscillations Ripple noise Linearity But all hopefully fixed! Module 0 128 channels board 8 channels module 8 outputs 8 Opamps & switches DAC Calolgic TTCRx SPAC2 Delay

21. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 21 Pulse shape before shaping Full DAC range 100 µV  1V Up to 5V pulses in 50 Ω Rise time < 2 ns Very small variation with DAC Undershoot Due to 50 Ω line between the switch and R0: should be 25 Ω Will be corrected HF Ringings: At small DAC values, due to parasitic package inductance DAC=100 µV DAC=1 mV 0dB DAC=10 mV 0dB DAC=0.1V -20dB DAC=1V -40dB

22. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 22 Pulse shape after shaping DAC=1V -80dB DAC=1mV -20dB DAC=100µV 0dB DAC=0µV Parasitic injected charge Peak of Qinj: Equivalent to DAC=30 µV At signal peak : Qinj< DAC = 15 µV Improvement by >10 compared to module 0 Qinj

23. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 23 Parasitic Injected Charge (PIC) Improvement Improvement : CH7 had the Nwell tied to 5V, as in the original configuration. Nwell of the other channels connected to the PMOS source to reduce the ringings => Clear improvement of Qinj On 8 channels Good uniformity of the PIC DAC=1mV -20dB CH7 : VB=+5V

24. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 24 DC and Pulse Linearity Measured on 3 gains 1-10-100 Pulse measurements In red After shaping (tp=50ns) DC current measur. In black With Keithley Example of problems DAC referenced to VP6 by mistake Bad 5Ω resistor brand Dynamic performance at the level to DC performance Gain 100Gain 10 Gain 1 Dc Linearity Residuals Pulse Linearity Residuals -0.05% Gain 1 -0.1% -0.05% Dac Ref corrected Bad R replaced DC linearity +0.05% +0.1% +0.05%

25. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 25 Designing the 128ch board 16 times replication of the 8 channels module Many tricky PCB layout details: to avoid coupling between digital and sensitive analog signals Difficult VP6 Distribution Connection between 5Ω and ref. VP6 taken for the DAC Must be uniform for all channels within 0.1% Can’t be shared between channels to minimize variation of amplitude with number of enabled channels Star configuration mandatory All VP6 lines equalized in length Common reference point on board center : dimension 2 x 1 cm = 1 mΩ => 5 layers necessary for the VP6 routing 150 mm 220 mm VP6 ref DAC

26. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 26 128 channels PCB layout Top layer : analog components Bottom layer: Digital components C5 layer:

27. 12 sept 2002N. Seguin-Moreau, 8th conference on LHC elctronics, COLMAR 27 CONCLUSION 2 prototypes of 128 channels calibration boards ready for tests of final ATLAS calorimeter electronics next october (1/2 crate) Production of 130 boards for ATLAS: Call for tenders at the beginning of 2003 Chips production DELAYS (600 already produced) DAC, SPAC, CALOGIC: to be produced on the same digital wafer in 2003 OP AMPs (28 000 to be produced before the end of 2002)