2. Mixed Signal Design Space Exploration through Analog Platforms F. De Bernardinis , P. Nuzzo , A. Sangiovanni Vincentelli   UC Berkeley  University of Pisa, Italy

3. 3 Outline Introduction Analog Platforms definition design flow Performance Models definition optimization of approximation process Mixed-Signal Case Study pipeline ADC design with platforms optimization and results Conclusions

4. 4 Introduction Mixed-Signal Design: heterogeneous problem to be coped at system level most remunerative tradeoffs across A/D interface scant attention in the past Platform Based Design originates as an answer to engineering and economic issues widely accepted in the design community moves design focus to composition of library elements Analog Design Flows limited synthesis capabilities struggle with device and circuit complexity

5. 5 Platform Based Design PBD is a meet-in-the-middle recursive process Application Architecture mapping mapping tools performance models level l+1 level l

6. 6 Analog Platforms : Definitions An Analog Platform is a library of components Platform Component Abstraction: input/output domains behavioral model feasible performance model validity laws The set of feasible performance models is described as abstract configuration parameters

7. 7 Analog Platforms : Definitions Example: level 0 OTA  0 is the set of V in (t) |V in | < 100 mV, f max = 2 MHz  0  is the set of MOS sizings  0  is the set of internal V and I  0  is the set of {V out (t), gain, IIP3, r out }  0  is the solution of device equations e.g. Spectre simulation  0  is obtained from Kirchhoff laws and maximum device ratings

8. 8 Analog Platforms : Definitions Example: level 1 OTA  1 =  0  1  = {x 1, x 2, x 3 }  1  is the set of {V out (t)}  1  is given by  1  is empty  1  is the set {a 1, a 3, f -3dB, noise, r out }  1 and  0 are strongly related in this case,  1 is a simple projection of  0

9. 9 Analog Platforms : Definitions Platform Instance Composition of plat- form components Defined by h  , υ  Υ ξ  Ξ, ζ   behavioral model  composition constraints

10. 10 Analog Platforms : Definitions Platform Instance Composition of plat- form components Defined by h  , υ  Υ ξ  Ξ, ζ   behavioral model  composition constraints Example Cap. array + Switch OTA FB C Sub-DAC FB Network

11. 11 Analog Platforms : Design Flow Successive refinement/abstraction steps Bottom-Up phase: define an abstraction ψ l that maps l into l+1 ψ l has to be conservative proceed to lower levels without iterations Simulation based performance generation can be conservative level l+1 level l

12. 12 Analog Platforms : Design Flow Successive refinement/abstraction process Top-down phase: optimization problem cost function  (y top ) application constraints platform constraints  (y top ) has to be minimized in Result: then, propagate down the stack mapping space 

13. 13 Performance Models Analog Platforms need a general and accurate scheme to represent performance models exploit a sampling scheme to approximate Image(φ y ()) use a classifier to generate W I bias Gain IIP3 Simulation  

14. 14 Performance Models The approach applies at all platform levels only requires of platform instances  () and φ y () Support Vector Machine classifiers [DAC03]: hyperplane classifiers in Hilbert spaces is a Gaussian RBF kernel  is the kernel parameter  i are a set of weights x i, y i are variable and function values  is a bias term heuristics to determine #samples and  false positives vs. false negatives Gain IIP3

15. 15 Refining the Configuration Space  Sampling is exponentially dependent on the size of  At platform levels>0 we have is constrained by At level 0, configuration spaces consist of physical parameters  κ = {I bias, V bias, W 1, L 1, …}    Circuit functionality limits  through: topological constraints physical constraints performance constraints Constraints effectively define

16. 16 Configuration Constraints Constraints can be represented as implicitly define Constraint relaxation f() cannot be expressed exactly analytical approximations to device behavior relax equalities to avoid configuration biasing  has to be estimated bounding analytical expression errors Configuration sampler in generate random solution to constraint system

17. 17 Analog Constraint Graphs Exploit bipartite graph representation [Donald] An ACG is an undirected bipartite graph ( , ,  ), where    are the design variables    are equations on design variables  ACGs represent under-constrained systems of equations with a set of inequalities A scheduling operation can be defined to provide efficient executable samplers in  M = W M /L M  B = W B /L B IBIB W2W2 L2L2 V GS2 22 W1W1 L1L1 V GS1 11

18. 18 Case Study: Pipeline ADC ADC DAC - ADC DAC - ADC DAC - ADC Digital Correction Logic 80 MS/s, 14 bit pipelined ADC, digitally calibrated, 0.13  m CMOS, STMicroelectronics Focus on first pipeline stage assume following stages ideal Mixed signal case study: first stage residue amplifier digital correction logic

19. 19 Level 1 Analog Platform Generate a Continuous Time Platform  is the set of MOS sizings and I bias  ={V out (t), gain, HD3, noise, SR, f -3dB, Power}  is is a Continuous Time behavioral model  requires C load to be 32pF Constraints on  [ISCAS05] based on approximate I DS, g m equations relaxed constraint formulation constraints on bias current, output range, stability, … SR OTA CTmodel

20. 20 Level 1 Analog Platform Folded Cascode topology defined similarly to telescopic same behavioral model Performance Model Generation exploit custom developed tools Client approximation process (Windows) Server simulation process (Linux) Parameter  Num. Sim.Time Telescopic  16 66 2,1349h Folded Cascode  17 66 2,83812h

21. 21 Characterization Results Performance Ranges ParameterTelescopicFolded Casc. Gain 26  920490  3100 Bandwidth (MHz) 1.5  8.90.29  2.7 RMS noise (mV) 1.4  6.22.8  29 Power (mW) 38  17056  180 Slew Rate (V/  s)400  2,400840  3,800 3D  Space projections Complex tradeoff gain bandwidth noise Model Accuracy 4% maximum relative error of AP models WRT Spectre

22. 22 Level 1 Analog Platform Switch component fixed sizing  contains one point determined by ADC speed and noise requirements Behavioral model charge injection noise linearity Accurate simulation data

23. 23 Level 1 Analog Platform Platform instance provides a Discrete Time (DT) model for the first pipeline stage Cap. array + Switch OTA FB C OTA model spans performance space of 2 topologies good accuracy maximum error WRT Spectre 5%

24. 24 Level 1 Digital Platform Digital post-process [Murmann03]: adjust gain linearize system Transfer Characteristic Estimation y = a 1 x+a 3 x 3 Characterization as a component bounds on accuracy of â 1 and â 3 simulate the algorithm: (a 1, a 3 )  (â 1, â 3 )  (P, a 1, a 3, â 1, â 3 )=1 Polynomial Inversion compute predictor/corrector implementation scheme performance model for accuracy:  (P, â 1, â 3 )=1 -0.0500.05 -0.4 0 0.4 V in (V) V res (V) 1 1 st Stage: LSB = 0.1 V FSR = 0.8 V AB

25. 25 Level 1 Digital Platform -0.0500.05 -0.4 0 0.4 V inin (V) V res (V) 1 1 st Stage: LSB = 0.1 V FSR = 0.8 V AB PolyInv PolyEstim μ1μ1 μ2μ2 â1â1 â3â3 y Platform library for digital enhancement simulation based characterization performance model  (P, a 1, a 3 )=1 Same flow for Analog and Digital Platforms

26. 26 Level 2 Mixed Signal Platform ADC - GDEC Cap. array + Switch OTA FB C -0.0500.05 -0.4 0 0.4 V in (V) V res (V) 1 1 st Stage: LSB = 0.1 V FSR = 0.8 V AB PolyInv PolyEstim μ1μ1 μ2μ2 â1â1 â3â3 y

27. 27 System Optimization Top-down optimization problem: minimize power consumption given linearity requirements minimum SNR Exploit simulated annealing stochastic global optimizer efficient behavioral and performance models

28. 28 Results Optimization performed in 18h based on simulation of ADC performance Results Performance Optimal (Telescopic) Mapped Folded Cascode Reference DNL (LSB)0.40.60.440.68 INL (LSB)0.10.210.150.26 SNR (dB)86.386.484.3 Power SHA (mW)52.552.6102146 Power OTA (mW)47.747.997146 A V0 2202141,1861,492 Bandwidth (MHz)3.3 0.791.35 V noise (mV rms)2.52.617.98.86 G7.37.277.87.94 Power GDEC 4.8 4.2-

29. 29 Conclusions A mixed signal design exploration methodology has been presented Analog platforms have been formally defined Simulation based performance models have been exploited: conservative approximations of feasible spaces approximated with SVMs A challenging ADC design has been presented analog and digital platforms the mixed signal design exploration has been solved with SA Results demonstrate the effectiveness of the approach automatic topology selection power reduced by 64% WRT reference design

30. 30 Thanks.