1. PSoC 3 / PSoC 5 101: Architecture Overview

2. Section Objectives Objectives, you will:
Understand the high-level architecture of PSoC 3 / PSoC 5
Understand the CPU, Digital, Analog & Programmable Routing / Interconnect Subsystems 2

3. PSoC 3 / PSoC 5 Platform Architecture
4 Main components of the PSoC Platform: CPU Subsystem, Digital Subsystem, Analog Subsystem and Programmable Routing and Interconnect
Let’s step through these…first, the CPU Subsystem

4. CPU Subsystem ARM Cortex-M3 Industry’s leading embedded CPU company
Broad support for middleware and applications
Up to 80 MHz; 100 DMIPS
Enhanced v7 ARM architecture:
Thumb2 Instruction Set
16- and 32-bit Instructions (no mode switching)
32-bit ALU; Hardware multiply and divide
Single cycle 3-stage pipeline; Harvard architecture
8051
Broad base of existing code and support
Up to 67 MHz; 33 MIPS
Single cycle instruction execution

5. CPU Subsystem High Performance Memory Flash memory with ECC
High ratio of SRAM to flash
EEPROM
Powerful DMA Engine
24-Channel Direct Memory Access
Access to all Digital and Analog Peripherals
CPU and DMA simultaneous access to independent SRAM blocks
On-Chip Debug and Trace
Industry standard JTAG/SWD (Serial Wire Debug)
On chip trace
NO MORE ICE

6. CPU Subsystem Clocking System Many Clock Sources
Internal Main Oscillator
External clock crystal input
External clock oscillator inputs
Clock doubler output
Internal low speed oscillator
External 32 kHZ crystal input
Dedicated 48 MHz USB clock
PLL output
16-bit Clock Dividers
8 Digital
4 Analog
PSoC Creator Configuration Wizard
PSoC Creator auto-derive clocking source/dividers
Eight 16-bit clock dividers generate digital system clocks for
general use in the digital system, as configured by the design’s
requirements. Digital system clocks can generate custom
clocks derived from any of the seven clock sources for any
purpose. Examples include baud rate generators, accurate
PWM periods, and timer clocks, as well as many others. If more
than eight digital clock dividers are required, the Universal
Digital Blocks (UDBs) and fixed function Timer/Counter/PWMs
can also generate clocks.
􀂄 Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, like ADCs and mixers. The
analog clock dividers include skew control to ensure that critical
analog events do not occur simultaneously with digital
switching events. This is done to reduce analog system noise.

7. CPU Subsystem Dedicated Communication Peripherals
Full Speed USB device
8 bidirectional data end points + 1 control end point
No external crystal required
Drivers in PSoC Creator for HID class devices
Full CAN 2.0b
16 RX buffers and 8 TX buffers
I2C master or slave
Data rate up to 400 kbps
Additional I2C slaves may be implemented in UDB array
New peripherals will be added as family members are added to the platform: Ethernet, HS USB, USB Host…

8. CPU Subsystem Power Management Industry’s Widest Operating Voltage
0.5V to 5.5V with full analog/digital capability
High Performance at 0.5V
PSoC 67 MHz; PSoC 72 MHz
3 Power Modes (Active, Sleep and Hibernate)
PSoC 5 at 72 MHz between 0.5v to 2.7v and back up to 80MHz from 2.7v to 5.5v

9. Designed for Low Power/Low Voltage
On-board DMA Controller
Direct memory transfer between peripherals offloads CPU operation, lowering power consumption
Highly configurable clock tree
Flexible, automated clock gating.
Universal Digital Blocks
Implement features in hardware that reduce CPU processing requirements, lowering power consumption
Cached Operations
Execution from flash memory is improved by caching instructions (PSoC 5 only)
Clock is automatically shut down for non-functioning parts…automated clock gating
Keys
DMA
UDBs
Shutdown CPU when/if not needed
Setup story of our low-power approach to design
Precise CPU frequencies
PLL allows 4,032 different frequencies; tunable power consumption
Integrated Analog, Digital and Communication Peripherals
Reduce external component counts and lower overall system power consumption

10. Low Power Modes Power Management Enabled in PSoC Creator
Current
(PSoC 3)
(PSoC 5)
Code execution
Digital resources available
Analog resources available
Clock sources available
Wakeup sources
Reset sources
Active
1.2 mA @ 6MHz
2 mA @ 6MHz
Yes
All
N/A
Sleep
1 uA
2 uA No
I2C
Comparator
Low Speed and 32 kHz Osc
IO, I2C, RTC,
sleep timer, comparator
XRES, LVD, WDR
Hibernate
200 nA
300 nA
None IO
XRES, LVD
PSoC1 Power:
Active: 6MHz)
Sleep: 3uA
Hibernate: N/A
Power Management Enabled in PSoC Creator
Provides easy to use control APIs for quick power management
Allows code and register manipulation for in-depth control

11. Digital Subsystem Universal Digital Block Array (UDBs)
Flexibility of a PLD integrated with a CPU
Provides hardware capability to implement components from a rich library of pre-built, documented, and characterized components in PSoC Creator
PSoC Creator will synthesize, place, and route components automatically.
Fine configuration granularity enables high silicon utilization
DSI routing mesh allows any function in the UDBs to communicate with any other on-chip function/GPIO pin with 8- to 32-bit data buses
32-bit PWM
GP Logic
16-bit PWM
UART #1
GP Logic GP
Logic
UART #2
UART #3 GP
Logic
LCD Segment Drive
GP Logic
What a UDB is (high-level)…step through the animation
Intelligent routing
Efficiency of the UDBs (part/pieces of each UDB can be used sep.)
Custom logic
Standard peripherals+custom logic
What’s the logic equivalent…~ gates per UDB, 24 UDBs in the larger chips
Suggested Flow: (a) go through 5 major points elaborating with info from slide notes. (b) Talk though two step animation. Step 1) PSoC Creator automatically places and routes components from PSoC Creator component library onto the UDB array and DSI routing mesh. Step 2) Customer control logic you may have implemented in verilog can take advantage of used used PLDs in UDBs (no waste). Point out the drawing is only conceptual
Flexibility of a PLD integrated with a CPU.
With a discrete PLD or FPGA logic would be consumed creating a bus interface to your MCU, not so in PSoC. Details on the following slide.
Provides access to a rich library of pre-build, documented, and characterized components in PSoC Creator
For example, UART, SPI, logic gages (AND, OR, NOR, etc) quadrature decoders, and more. The UDB array may also be used to implement additional I2C, timer, counter, and PWM functions if dedicated and optimized peripherals have already been used.
Fine configuration granularity enables high silicon utilization.
When we say that a component uses 2 UDBs it is unlikely that 100% of those 2 UDBs are actually used. For example, 2 DUBs maybe used use to implement a 16-bit shift register, but, the PLD in those UDBs are not used. PSoC Creator keeps track of this usage information allow for example a users custom Verilog to use the PLDs that are not used by the 16-bit shift register. This is what we mean by fine granularity of the configuration.
Supports user generated Verilog control logic (PSoC Creator takes care of synthesis, placement, and routing.).
DSI Routing mesh allows any function in the UDBs to communicate with another on-chip function or any GPIO pin.
NOTE: PSoC Creator today does not have a 32-bit PWM component, however silicon supports this capability. A customer or Cypress could create a 32-bit PWM component that will run inside the device.
I2C Slave
16-bit Shift Reg.
SPI Master
GP Logic

12. Digital Subsystem Optimized 16-bit Timer/Counter/PWM Blocks
Provides nearly all of the features of a UDB based timer, counter, or PWM
PSoC Creator provides easy access to these flexible blocks
Each block may be configured as either a full featured 16-bit Timer, Counter, or PWM
Programmable options
Clock, enable, reset, capture, kill from any pin or digital signal on chip
Independent control of terminal count, interrupt, compare, reset, enable, capture, and kill synchronization
Plus
Configurable to measure pulse widths or periods
Buffered PWM with dead band and kill
Optimized 16-bit Timer/Counter/PWM Blocks
We have static stuff, very easy to use…next
Provides nearly all of the features of a UDB based timer, counter, or PWM in an area optimized peripheral.
PSoC Creator provides easy access to these flexible blocks.
Each block may be configured as either a full featured 16-bit Timer, Counter, or PWM.
PSoC Flexibility
Clock, enable, reset, capture, kill from any pin or digital signal on chip.
Independent control of terminal count, interrupt, compare, reset, enable, capture, and kill synchronization.
Plus
Configurable to measure pulse widths or periods.
Buffered PWM with dead band and kill

13. Analog Subsystem Configurable Analog System
Flexible Routing: All GPIO are Analog Input/Output
+/- 0.1% Internal Reference Voltage
Delta-Sigma ADC: Up to 20-bit resolution
16-bit at 48 ksps or 12-bit at 192 ksps
SAR ADC: 12-bit at 1 Msps
DACs: 8 – 10-bit resolution, current and voltage mode
Low Power Comparators
Opamps (25 mA output buffers)
Programmable Analog Blocks
Configurable PGA (up to x50), Mixer, Trans-Impedance Amplifier, Sample and Hold
Digital Filter Block: Implement HW IIR and FIR filters
CapSense Touch Sensing enabled
Configurable Analog System
Some chips with lots or less analog…
Roadmap to analog filtering using the prog-analog blocks
Use separate module and details from SCON content
Key message is that this is portfolio of analog – scales with various products
The PSoC3/5 architecture has a huge portfolio of analog IP. Exact configuration depends on the product family.
20-bit Del Sig samples at 180 sps

14. Programmable Routing/Interconnect
Input / Output System
Up to 4 separate I/O voltage domains
Interface with multiple devices using one PSoC 3 / PSoC 5 device
Three types of I/O
GPIO, SIO, USBIO
Any GPIO to any peripheral routing
Wakeup on analog, digital or I2C match
Programmable slew rate reduces power and noise
8 different configurable drive modes
Programmable input threshold capability for SIO
Auto and custom/lock-able routing in PSoC Creator

15. PSoC 3 / PSoC 5 Platform Architecture
That is the PSoC3/5 Platform Architecture/Summary.

16. Review
You should now:
Understand the high-level architecture of PSoC 3 / PSoC 5
Understand the CPU, Digital, Analog & Programmable Routing / Interconnect Subsystems 16

17. Lab 101: My First PSoC 3 Digital Design17

18. Lab Objectives Objectives: Blink an LED on the PSoC First Touch Kit
Experience the PSoC Creator Design Flow 18

19. Step 1: Start PSoC Creator19

20. Step 2: Create a New Project20

21. Step 3: Place/Configure Digital Pin21

22. Step 3: Place/Configure Digital Pin22

23. Step 4: Configure PSoC I/O23

24. Step 5: Add main.c Code 24

25. Step 5: Add main.c Code 25

26. Step 6: Build Project 26

27. Step 7: Program/Debug 27

28. Step 8: Debug 28

29. PSoC 3 / PSoC 5 101: PSoC Creator Design Flow29

30. Section Objectives Objectives, you will be able to:
Follow the PSoC Creator Design Flow and develop projects
Find and use the tools available within the software IDE
Compile, build and program PSoC 3 / PSoC 5 applications
Debug PSoC 3 / PSoC 5 applications 30

31. PSoC Creator Design Flow
Configure
Start a new project
Place components
Configure components
Connect components
Develop
Build hardware design and generate component APIs
Write application code utilizing component APIs
Compile, build and program
Debug
Perform in-circuit debug using PSoC Creator
Reuse
Capture working hardware/software designs as your own components for future use 31

32. Open PSoC Creator

33. PSoC Creator Software

34. Create a new project Select the platform Name the design
Select the device*
Select the sheet template*
* Optional steps
The Advanced button allows for selection of sheet template as well as device selection. From the Advanced button the device selector maybe launched.
Not really important to make your device selection here, just the platform selection (PSoC3 or PSoC5) is what’s required…you can change your device at any time…including platform, but starting with one platform will establish what components you have to begin with.

35. PSoC Creator Design Canvas
Creating a new project will add main.c and device.h to the project. Device.h has an include of project.h. Project.h is a generated file based on your design.

36. Component Catalog Catalog Folders Catalog Preview Datasheet access
Analog
ADC
Amplifier
DAC
Digital
Registers
Functions
Logic
Communication
Display
System
Catalog Preview
Datasheet access

37. Adding Components to a Design

38. Pins, Logic and Clock Components

39. Component Configuration
Double-click to open component configuration dialogs

40. Component Data Sheets Contents: Features
General description of component
When to use component
Input/Output connections
Parameters and setup
Application Programming Interface
Sample firmware source code
Functional description
DC and AC electrical characteristics

41. Design-Wide Resource Manager (.cydwr)
Clocks
Interrupts
Set priority and vector
DMA
Manage DMA channels
System
Debug, boot parameters, sleep mode API generation, etc.
Directives
Over-ride placement defaults
Pins
Map I/O to physical pins and ports
Over-ride default selections

42. Interrupts
Priority may be changed Defaults to 7 (lowest priority)

43. DMA
Priority may be changed Defaults to 2 (0 & 1 can consume 100% of bandwidth)

44. System
System settings Debug settings Voltage Configuration

45. System Clocking Tree

46. Clock Configurations Clocks are allocated to slots in the clock tree
8 digital, 4 analog
Clocks have software APIs
Reuse existing clocks to preserve resources
Note: Setting or customizing a clock for your application is as simple as adding a clock component and writing in the specific clock speed you want; don’t worry about dividers, clock sources or any other details.

47. Pin Editor

48. Connecting Components

49. Build Hardware Design
Generates component APIs

50. Build Process Generate a Configuration Design Elaboration Netlisting
Verilog
Logic Synthesis
Technology Mapping
Analog Place and Route
Digital Packing
Digital Placement
Digital Routing
<…there’s more…>
The first task of the build process is to create a configuration of your device. The steps to achieve this are: Elaboration, Netlisting, Verilog, Logic Synthesis,VH2, Tech Mapping, Analog Place and Route, Digital Packing, Digital Placement, Digital routing,

51. Build Process API Generation Compilation Configuration Generation
Configuration Verification
Next comes the API generation, configuration generation and verification.

52. Development Files Core Cypress Libraries (CyLib)
Registers, macros, types (cytypes)
Component addressing (cyfitter)
APIs are the first place to go for register access.

53. Supported Compilers Free Bundled compiler options
PSoC 3: Cypress-Edition Keil™ CA51 Compiler Kit
PSoC 5: GNU/CodeSourcery Sourcery G++™ Lite
No code size restrictions, not board-locked, no time limit
Fully integrated including full debugging support
Upgrade, more optimization/compiler-support options
PSoC 3: Keil CA51™ Compiler Kit
PSoC 5: Keil RealView® Microcontroller Development Kit
Higher levels of optimization
Direct support from the compiler vendor
Upgrade Compiler Pricing
Set and managed by our 3rd party partner, Keil
Already own these compilers? No need to buy another license!
Keil CA51 Compiler Kit ~$2,000
Keil RealView MDK ~$3,000-5,000
GNU

54. Integrated Debugger JTAG and SWD connection
All devices support debug
MiniProg3 programmer / debugger
Control execution with menus, buttons and keys
Full set of debug windows
Locals, register, call stack, watch (4), memory (4)
C source and assembler
Components
Set breakpoints in Source Editor

55. Debugger Windows

56. MiniProg3 Program PSoC 1 devices Program/Debug PSoC 3 / PSoC 5 devices
Standard 50mil connector
nTRST/XRES pin is used as the device reset (XRES) by default
nTRST is JTAG specific and rarely used
2x5 50mil ISSP/JTAG/SWD/ SWV/TracePort ribbon cable and connector
ISSP connector
The MiniProg3 is designed to replace the current PSoC1 MiniProg device in all future kits. MiniProg3 has been updated to support all debug and programming features of PSoC3/5 devices as well as provide improved features for PSoC1 devices.
Key new features of MiniProg3 include
2x5 50mil connector for JTAG and SWD interfaces. Connector is smallest low cost and easily sourced connector meeting JTAG/SWD requirements. Ribbon cable provides flexibility in connector location
Increased data throughput. Full speed USB device
Programmable supply voltage for PSoC1 devices. Powering of PSoC3/5 devices is not recommended unless all power supplies are tied together or the user is otherwise sure the power system is compatible.
Future trace support for ARM devices
Ribbon cable length is bus speed and target board layout dependant. Ribbon cable Length to max speed suggestions are as follows.
3” (7.5 cm) - 8 MHz (Standard MiniProg3 ribbon cable)
6” (14 cm) – 4 MHz
12” (30cm) – 2 MHz
24” (30cm) – 1 MHz 56

57. PSoC Development Kit (CY8CKIT-001)
Supports all PSoC architectures via processor modules
Integrated support of all required and optional chip connections
MiniProg3 should not supply power to PSoC Development Kit
Independent digital, analog and IO supply rails (current measurement supported)
3.3V, 5.0V and adjustable 1.8V–5.0V regulators
RS-232
Three expansion ports support 28 IO each + 45 IO
USB for target
PSoC Processor Modules
RF Module Radio header
1 Pot, 2 buttons, 4 LEDs, 2x16 LCD
CapSense Slider & Buttons

58. Review You should now be able to:
Follow the PSoC Creator Design Flow and develop projects
Find and use the tools available within the software IDE
Compile, build and program PSoC 3 / PSoC 5 applications
Debug PSoC 3 / PSoC 5 applications 58