1. A High-Speed Analog Min-Sum Iterative Decoder Saied Hemati, Amir H. Banihashemi, and Calvin Plett Carleton University, Ottawa, Canada

2. Outline  Introduction  Min-Sum Decoding Algorithm  Basic Modules and Circuits  Analog Min-Sum Decoder for a (32,8) Code  Measurement Results  Conclusion

3. Introduction Why analog?  Lower power/speed ratio  Lower noise generation  Lower area consumption  Better decoding performance (Hemati and Banihashemi, 2003) Previous Work: - Loeliger et al., 2001 - Mondragon-Torres et al., 2003 - Gaudet et al., 2003 - Morez et al., 2000 - Hemati et al., 2003 - Winstead et al., 2004 - Amat et al., 2004

4.  Other Approaches: - are b ased on belief propagation (BP) - have a d ifferential multiplier as the basic processing module - use the well-known Gilbert differential multiplier  Linearity of the Gilbert multiplier relies on the exponential behavior of bipolar (or quasi-bipolar weakly inverted CMOS) transistors.  Bipolar technology is expensive and weakly inverted CMOS transistors are slow.  Multiple-input modules are constructed by cascading two-input Gilbert multiplier modules.

5.  Our Approach: - is based on min-sum (MS) - does not require an estimate of the noise power - is more robust against quantization noise - is based on current mirrors - multiple-input modules can be directly implemented  There are simple modifications of MS that can perform very close to BP.

6. Min-sum Decoding Algorithm Basic operations in MS: mvmv V C

7. Basic Modules and Circuits Current buffers duplicate input current at the output with flipped sign

8. Variable Nodes Basic modules and circuits

9. Check Nodes Basic Modules and Circuits

10. An RTAS module, (a) current rectifier, (b) sign extractor Basic Modules and Circuits

11. (a) A current-mirror, (b) a current-mode 3- input max WTA. Basic Modules and Circuits (a) (b)

12. ASTR module Basic Modules and Circuits

13. Analog MS Decoder for a (32,8) Code Tanner graph of the code

14. Architecture of the implemented chip Analog MS Decoder for a (32,8) Code

15. Microphotograph of the fabricated chip Analog MS Decoder for a (32,8) Code

16. 16/21 Measurement Results

18. TechnologyThroughput (Mb/s) Core (mm 2 ) Power (mW) Supply (V) TransistorsPower/ speed Code Lustenberger et al. 0.8µm BiCMOS 1002.89505BJT ( 940) p-MOS (650) 0.5 nJ/b (18,9,5) tailbiting Moerz et al. ‎ 0.25µm BiCMOS 3200.12203.3BJT ( 441) n-MOS (356) 0.06 nJ/b (16,8,3) tailbiting Gaudet et al.0.35µm CMOS (subthreshold) 13.31.321853.3CMOS13.9 nJ/b Turbo Code (length 16) Winstead et al. ‎ 0.5µm CMOS (subthreshold) 2 (0.02) 0.821 (0.016) 3.3CMOS0.5 nJ/b (0.8nJ/b) (8,4,4) Amat et al. ‎ 0.35µm CMOS (subthreshold) 24.110.33.3CMOS (26,000) 5.2 nJ/b Turbo Code (length 40) This work0.18µm CMOS 240.5751.8CMOS (18,800) 0.2 nJ/b (32,8,10) Code

19. Conclusion  A modular methodology was proposed for designing CMOS analog MS iterative decoders.  The modules are based on current mirrors and therefore our approach can be used for implementing analog MS decoders in advanced bipolar and CMOS technologies.  A proof-of-concept analog MS decoder chip for a (32,8) regular LDPC code was fabricated and tested.  In low-SNR region, measurement results are close to the simulation results based on SR-MS algorithm.