1. Power/Thermal Impact of Network Computing Cisco Router Technology Symposium Evaldo Miranda & Laurence McGarry

2. 2 Source : Intel – 2003 Spring IDF Data Flow == Power / Thermal Flow

3. 3 “Moore’s Law” on Processor Power Source : Intel Technology Journal, Vol 6, Issue 2

4. 4 Source : Kenneth Goodson, Stanford University

5. 5 The Power Supply Chain Generation Source Transmission Data Center Shelf/Rack System Line Card Application Load; Processor, DSP, Memory Graphics 100% -5%-20% (Cooling) -10% AC/DC -10% DC-DC ~55% - Electrical Pwr ~30% - Processing Pwr

6. 6 Total Cost of Ownership

7. 7 Trends for Power Power Delivery & Utilization for Analog Processing ADC bottleneck: fast & highly linear gain element. 50-70% of total pipeline ADC power is consumed by interstage amplifiers Redundancy (RSD arithmetic) helps tolerate large sub A/D errors [Lewis, 1987] “Digital calibration“ removes D/A and linear gain error by adjusting digital weights [Karanicolas, 1993] Pipeline ADC

8. 8 Trends for Power Power Delivery & Utilization for Analog Processing + Lower Noise + Increased Signal Range + Lower Power + Faster – Nonlinear  Signal Processing used to linearize! “Open loop“Precision Amplifier [Murmann 03] : Open-Loop Amplification

9. 9 [Iroga/Murmann] : Digital Nonlinearity Compensation Trends for Power Power Delivery & Utilization for Analog Processing

10. 10 Trends for Power Power Delivery & Utilization for Analog Processing 4X 16X [Iroga/Murmann 05] : 12-b, 75-MS/s ADC implemented in 0.35um CMOS Stage1 Power Breakdown

11. 11  The area of digital is cut in half with every new generation  The area of analog is reduced by 20~30% with every new generation  The cost of digital is cut in half every 2~3 years  The cost of analog is cut in half every 4~8 years Ref: Anton Bakker - Analog Devices Inc.  Moore’s Law is different for Analog and Digital Trends for Power

12. 12 Layout comparison in 0.25um CMOS 10pF Bondpad + ESD 12-bit ADC Trends for Power

13. 13 Buck Converter I Supply Computing Load Fault / OK REF PWM V T V T V T Pwr Losses T

14. 14 Buck Converter II Monitor - Control - Adapt RE F Supply Computing Load V T V T V T DPWM Pwr Losses Fault / OK PWM T

15. 15 Smart Power Chain Block Diagram Rectifier Drivers PWM Switch Bridge LC Filter OrFET PFC Ctrl Rectifier & PFC POL Switchers SwitchersPOL LDOLDO VRM for PCs VRM for PCs Hot Swap Hot Swap Sequencers Margining Sequencers Margining Hot Swap Hot Swap Sequencers Margining Sequencers Margining BatteryChargersBatteryChargers Power Management Units Power Management Units Delivering Power Through Information SMBus / SST / PMBus I2C/SMBus Micro-ControllerMicro-Controller Secondary-Side Controller & Sync Rect Secondary-Side Controller & Sync Rect Drivers Drivers Temp Sensor & Fan Controllers Temp

16. 16 Summary and Conclusions  Proliferation of computing/networking/communications applications resulting in extreme and bounded power density demands on supporting devices/systems  Falling cost of digital technology allows availability of digital techniques to optimize/improve system functions Adaptable/reconfigurable regulators for efficient energy transfer Utilize information about the source & load Use System level management USE YOUR “BUCK” CONVERTER EFFICIENTLY

17. 17 Presented By: Evaldo Martins Miranda Power & Thermal Design Manager Laurence McGarry Power & Thermal Marketing Manager Analog Devices, Inc. 3550 North First St San Jose – CA 95134 evaldo.miranda@analog.com Laurence.mcgarry@analog.com

18. 18 Back-up

19. 19 Power/Thermal Impact of Network Computing  Growth of fixed and mobile devices linked by a network processing voice, data and video. Moore’s law on Power and Thermals from processors to buildings for data centers Demand for power and cooling capacity on existing data centers and server farms.  Power Management in Processors Fab processes (eg: strained silicon and low leakage oxides) Device structure (eg: 3D devices) Circuit designs (eg: voltage, frequency and body switching) Architecture (eg: multi-core and intelligent timing/scheduling/multi-tasking)  Power Management for Computing Platforms (HW Board level and Systems) Increase efficiency of passive devices and their use: Drivers, FETs, Inductors (coupled) Improve Thermal solutions: bigger heat sinks, fans, heat–pipes and liquid cooling Use Multi-phase Voltage Regulator up to 130A per processor w/ up to 20kW per rack Multiple power rails  Power Management Opportunities (Platform Systems Solutions) Remote Monitoring/Control of networked systems Balancing computing load & data handling traffic Security & Virtualization  Rethinking Power Conversion (+ Communication) Increase efficiency/utilization/reliability of platforms/racks & Reduce cooling Efficiency under varying load, ambient and fault conditions while reducing component count and adjusting for component aging, degradation and failure prediction.

20. 20 Digital Cost Trends Ref: Y Borodovsky Intel SPIE Microlithography 2006

21. 21 Trends for Power Power Delivery & Utilization for Digital Processing

22. 22 Trends for Power Power Delivery & Utilization for Analog Processing 0 1 0123456789101112 t/  V out /V ref [Iroga/Murmann 05] : Incomplete Settling

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25. 25 Pentium 4 Thermal Solution

26. 26 VCR – 35dBA DVD – 29dBA

27. 27 Redundant Server Power Supply 12V@50A (600W)

28. 28 Buck Converter I Supply Computing Load Fault / OK RE F PWM V T V T V T Pwr Losses