1. 1/6 Aadithya V. Karthik Feb 2014, BEARS lightning talk, Berkeley ABCD: “Booleanizing” Analog Systems for Verifying Chips Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert Brayton, and Jaijeet Roychowdhury EECS Dept., The University of California, Berkeley Feb 2014, BEARS, Berkeley

2. 2/6 Aadithya V. Karthik Feb 2014, BEARS lightning talk, Berkeley The Problem: Verifying a Chip Specification Chip designers Chip

3. 3/6 Aadithya V. Karthik Feb 2014, BEARS lightning talk, Berkeley Surrounded by Digital Logic Example: SERDES Analog parts PLL CDRI/O The Problem: AMS Verification  Want to verify complete system o e.g., eye opening height > 1V?  Proof or counter-example needed >1V

4. 4/6 Aadithya V. Karthik Feb 2014, BEARS lightning talk, Berkeley Our approach: “Booleanize” the analog parts Best verification tools = all Boolean, no continuous Digital components Verification tools accept Analog components Challenge: Analog models Digital models + Continuous Boolean (don't mix) SAR-ADC Boolean T/H approximation Boolean comparator approximation Boolean DAC approximation ALL BOOLEAN Formal verification, high-speed simulation, test pattern generation,... ABCD: Boolean approximation … for the full combined system! Fast

5. 5/6 Aadithya V. Karthik Feb 2014, BEARS lightning talk, Berkeley ABCD in action Analog Circuit Purely Boolean Model ABCD Bit Sequence Example: Channel + Equalizer

6. 6/6 Aadithya V. Karthik Feb 2014, BEARS lightning talk, Berkeley Circuits Successfully Booleanized Charge pump Equalizer Delay line Power grid SAR-ADC I/O signaling system