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Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver VLSI Design Using PC-Based Tools Cherrice Traver Union College Schenectady,

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Presentation on theme: "Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver VLSI Design Using PC-Based Tools Cherrice Traver Union College Schenectady,"— Presentation transcript:

1 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver VLSI Design Using PC-Based Tools Cherrice Traver Union College Schenectady, NY

2 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Why use PC-based tools?

3 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Outline Tanner Research Tools for Education Practical issues Tool flow and capabilities Example use Curriculum examples

4 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Practical Issues System Requirements Minimum requirements 100 MHz PCs, 32M RAM Recommended 500 MHz PCs, 256M RAM 3-button mouse

5 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Practical Issues Installation Tool installation - Install-Shield Wizard License server –Sentinel LM on NT Server –Floating individual tool licenses

6 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Practical Issues Tool Choices L-EditDRC EXT SPR L-Edit Pro Tspice S-Edit W-Edit T-Spice Pro Design Pro CMOS Libraries Tanner Tools Pro

7 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Practical Issues Cost and Maintenance Educational pricing Quantity pricing Free support for 60 days No annual maintenance fee required 15% maintenance fee per year for updates and continued support

8 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Practical Issues Documentation Help MenuIndexed PDF Manual

9 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Contact Information Janice Barthelemy Account Manager janice@tanner.com Tanner EDA 2650 East Foothill Blvd. Pasadena, CA 91107 Toll free (877) 325-2223 Fax (626) 792-0300 www.tanner.com

10 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Simplified Tanner Tool Flow S-Edit TM Schematic Editor T-Spice TM Circuit Simulator L-Edit TM Full Custom Layout Editor W-Edit TM Waveform Viewer GDS II & CIF

11 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Overview of Examples Layout Editor - L-Edit Schematic Editor - S-Edit Standard Cell Place and Route - SPR Spice simulator - T-Spice

12 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver L-Edit: Tool Flow L-Edit TM Full Custom Layout Editor L-Edit/SPR TM Standard Cell Place & Route L-Edit/Extract TM General Device Extractor L-Edit/DRC TM On-line Design Rule Checker Cross Section Viewer Layout Libraries SCMOSLib... S-Edit TM T-Spice TM

13 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver L-Edit: Layout Editor Features

14 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver L-Edit: Example CMOS Inverter Layout Editing DRC Cross Section Viewing Extract Spice File

15 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver S-Edit: Tool Flow S-Edit TM Schematic Editor Technology Mapping Library SCMOS... SchemLib TM Technology Independent Library T-Spice TM L-Edit TM SPR NetTran netlist extract

16 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver S-Edit: Schematic Editor Features

17 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver S-Edit: Example Full Adder Circuit Schematic Drawing Spice Export Tanner Place and Route Export

18 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver SPR: Tool Flow L-Edit TM Full Custom Layout Editor L-Edit/SPR TM Standard Cell Place & Route S-Edit TM.tpr file Layout Libraries SCMOSLib...

19 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver SPR: Example Full Adder Circuit L-Edit - Place and Route Core + Padframe Extract Spice Circuit

20 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver T-Spice and W-edit: Tool Flow T-Spice TM Circuit Simulator W-Edit TM Waveform Viewer S-Edit TM L-Edit TM netlist extract device extract

21 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver T-Spice and W-edit: Features Menu-based command insertion Integrated W-Edit waveform viewer Circuit Probing from S-Edit

22 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver T-Spice and W-edit: Example Full Adder simulation –Simulation of schematic netlist –Waveform probing –Simulation of extracted layout

23 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Tool Integration in VLSI Design Course Laboratories –Tool use –Reinforcement of lecture topics Project –Behavior --> Layout design experience

24 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Laboratories Lab 1 - L-Edit/T-Spice Extract/simulate NAND gate Layout/extract/simulate inverter Lab 2 - L-Edit/T-Spice Manual placement/routing standard cells Manual stick diagrams Extraction/simulation Lab 3 - S-Edit/L-Edit/SPR/T-Spice Schematic capture - netlist simulation Standard cell place/route

25 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Kitchen Timer Project from Modern VLSI Design: Systems on Silicon, Wayne Wolf

26 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Buzz Circuit Schematic Given - Lab Exercise

27 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Display Circuit Block Diagram Given - Lab Exercise

28 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Controller Specified by state diagram and VHDL model Logic simulation outputs provided

29 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Timer

30 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Support Provided VHDL “Golden” behavioral model Simulation output results Lots of guidance on debugging

31 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Top Level Schematic

32 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Kitchen Timer Chip Statistics 600 Gates 8000 Transistors Layout area: 1550 um x 1375 um

33 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Final Layout

34 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver MOSIS Fabrication Pads provided Flatten layout Export CIF file

35 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Other Past Designs Using Tanner Tools Quadrature Decoder http://doc.union.edu/154/Quad.decode.project/index.html Simple Floating-Point Multiplier http://doc.union.edu/154/Mult.project/mult.project.html

36 Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver Conclusion Ease of Installation/Maintenance Reasonable Design Flow Good Interface for MOSIS Fabrication

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