1. Asynchronous comparator design
Motivation
Background: Sync and Async comparators
Delay-insensitive carry-lookahead
comparators
Complexity Analysis
Conclusions

2. Motivation operations in digital systems.
Comparison is one of the most important
operations in digital systems.
Comparators are used in ALUs, cache memory,
MMU and data hazard detection.
Integer comparison: use an integer adder.
Problem: addition time > comparison time.
High speed comparison is needed.

3. Background: Binary Comparison
Worst case: A=B A: B:
Best case: A>B B:
Comparators can perform average case behavior

4. Background
Ripple-Carry Comparator(Sync):
Flow table specification:

5. Background
Delay-Insensitive Ripple-Carry Comparator:
Flow table:

6. Background Ripple-Carry Comparator: Logic complexity: O(n)
Time complexity: O(n)
Delay-Insensitive Ripple-Carry Comparator:
Time complexity: O(1)

7. Carry-Lookahead Comparators
RCC requires n stage-propagation delays.
Use carry-lookahead comparators(CLC).
CLCs:
Logic complexity: O(n)
Time complexity: O(log n)

8. 8-bit carry-lookahead
comparator

11. DI Carry-Lookahead Comparator
Delay-Insensitive Carry-Lookahead Comparators
may be implemented by using delay-insensitive
code.
1. dual-rail signaling: input bits
2. one-hot code: internal signals, s, g, e (S, G, E).
S: smaller (A<B)
G: greater (A>B)
E: equal (A=B)

17. CMOS Implementation
DI P-module:

18. CMOS Implementation
DI I-module:

19. CMOS Implementation
DI SI-module: 3 2-input AND gates.

20. CMOS Implementation Speed-up circuits for S and G signals: Dynamic OR
gates.

21. CMOS Implementation
Speed-up circuits for E signals:
Dynamic OR gate:

22. SPICE Simulation: SPICE Simulation contains two parts:
Random number inputs:
10000 random generated input pairs
Statistical data:
running examples on a 32-bit ARM
emulator

23. SPICE Simulation: Random number inputs:
10000 random generated input pairs
a. RCC: 32.4ns
b. CLC: 6.2ns

24. SPICE Simulation:
Confidence Limits:

25. SPICE Simulation:
Confidence Limits:

26. SPICE Simulation:
Distribution of typical-case comparisons:

29. SPICE Simulation:
SPICE simulation
results:
dynamic traces

30. Conclusions A new pratical design of DI comparator. Theoretically,
Logic Complexity:((n)).
Time Complexity:((1)).
Reality:
more than 2 times faster than its sync
counterpart with 80% usable clock.
Suitable for VLSI implementation.