2. An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization Carlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, and Patrick McNamara PDF Solutions Inc. DAC 2005, Anaheim, CA

3. Technology Roadmap Challenges 65nm  Lithography  OPC/PSM integr. w/ photo-window  Front-end/Transistor  Layout dependent performance  Parametric variation 65nm  Lithography  OPC/PSM integr. w/ photo-window  Front-end/Transistor  Layout dependent performance  Parametric variation 45nm  Lithography  Layout pattern dependence  Immersion litho,  OPC/PSM integration w/ photo window  Front end/Transistor  New gate/oxide architectures  Reliability 45nm  Lithography  Layout pattern dependence  Immersion litho,  OPC/PSM integration w/ photo window  Front end/Transistor  New gate/oxide architectures  Reliability 90nm  Back-end integration  Low-k  CMP  Product ramp issues  Yield vs. performance 90nm  Back-end integration  Low-k  CMP  Product ramp issues  Yield vs. performance

4. Random defects are no longer the dominant yield loss mechanism Random defects are no longer the dominant yield loss mechanism –Yields are limited by design features The Evolution of Product Yields

5. From Reactive to Proactive DFM: A Copernican Revolution… Accurate Yield Models Characterized in Silicon Accurate Yield Models Characterized in Silicon Fully integrated in standard design tools and flows Fully integrated in standard design tools and flows Design rules guarantee yield!…well, not really… Design rules guarantee yield!…well, not really… …then recommended rules …then recommended rules …and opportunistic design data base post-processing to enforce them …and opportunistic design data base post-processing to enforce them Yield Revolved Around Rules Yield Models are the driving force in the DFM universe

6. Rule-based DFM? MUX4X1AFY_Y1 - 20 tracks MUX4X1AFY_COY4 - 25 tracks MUX4X1AFY_PMSY4 - 21 tracks MUX4X1AFY1_Y16 - 27 tracks 32 FPB 19 FPB 20 FPB 25 FPB

7. Reactive vs. Proactive DFM DRM SynthesisPlace&routeDesignDesign IP lib. Design Floorplan SPICEDesignDesign VerificationVerification VerificationVerification Timing & SI Physical Formal DFM sign-off DFM sign-off DFM & Manufacturing OPC/RET Dummy Fill MDP DFM Optimizations DFM Optimizations Mask Making DRM Yield –aware Synthesis Yield –aware Synthesis Yield-aware Place&route Yield-aware Place&routeDesignDesign IP lib. Design Yield Aware Floorplan SPICEDesignDesign VerificationVerification DFM & Manufacturing OPC/RET Dummy Fill MDP DFM Tuning DFM Tuning Mask Making Manufacturing Facility VerificationVerification Statistical Timing & SI Physical Formal DFM sign-off DFM sign-off

8. Proactive DFM Designer access to process data is limited Designer access to process data is limited –DFM today is Reactive –Increased design cycle time –Risky design feature changes –Misaligned mask GDSII and design database DFM needs to be Proactive DFM needs to be Proactive –Up-front accurate process characterization –Occurring early in the design flow –Model based IP characterization –Manufacturable-by-construction designs Designer access to process data is limited Designer access to process data is limited –DFM today is Reactive –Increased design cycle time –Risky design feature changes –Misaligned mask GDSII and design database DFM needs to be Proactive DFM needs to be Proactive –Up-front accurate process characterization –Occurring early in the design flow –Model based IP characterization –Manufacturable-by-construction designs

9. DFM characterization Of IP libraries Characterize IP library for yield (.pdfm) Characterize IP library for yield (.pdfm) –Extract design attributes of yield models –Include random, design systematic and litho effects New yield library view (.pdfm) New yield library view (.pdfm) Enable hierarchical large capacity DFM chip analysis Enable hierarchical large capacity DFM chip analysis Library GDS Process FR (D 0, ) Yield Extractions Design Attributes ACC.pdfm Library GDS Process Margins and Litho calibration data Lithography Simulator Libra ry YIMP ACC.pdfm Context Generation Golden OPC/RET RANDOM Design SYSTEMATIC Litho Process Window

10. Random Yield Loss: Physical Mechanisms Contact and via opens due to formation defectivity Active, poly and metal shorts and opens due to particle defects Random Yield Loss Mechanisms Type Material opens Material shorts

11. Random Yield Loss: Test Structures Extract Metal layer open and short defectivity Extract Metal layer open and short defectivity Extract Metal layer open and short Defect Size Distribution (DSD) Extract Metal layer open and short Defect Size Distribution (DSD)

12. Systematic Yield Loss: Physical Mechanisms Misalignment, line-ends/borders Contact/via opens due to local neighborhood effects (e.g. pitch/hole size) Leakage from STI related stress Impact of micro/macro loading design rule marginalities Systematic Yield Loss Mechanisms Type

13. Systematic Yield Loss: Test Structures Without NeighborhoodWith Neighborhood STI M1 To Pad ATo Pad BTo Pad C N+ PWL N+ P+

14. Printability Yield Loss: Physical Mechanisms Material opens Poor contact coverage due to misalignment and defocus/pull back Systematic Yield Loss Mechanisms Type Poly/Metal shorts

15. Printability Yield Loss: Modeling LayoutMetric Misalignment Mask Error Defocus Exposure Yield Loss coverage

16. The.pdfm View Library characterized to generate manufacturability view (.pdfm) Library characterized to generate manufacturability view (.pdfm) –Random and design systematic yield –Litho process window Using calibrated yield models Using calibrated yield models Multi-layer litho process window incorporated Multi-layer litho process window incorporated Cell Characteristic Library View Lay out GDS Schematic SPICE Netlist P&R Footprint LEF Performance.lib Logic Function Verilog Power Noise …… Manufacturability. pDFM

17. Application: IP library DFM Quality Analysis Yield sensitivity analysis Optimal design depends on process corner Optimal design depends on process corner –Ex NAND2: Y5, Y6, Y1, Y4 Best becomes worst at different process corner Best becomes worst at different process corner –Ex NAND2: Y1_m1opens vs. Y1_m1shorts DFM Sensitivity depends on layout attributes DFM Sensitivity depends on layout attributes –M1 more sensitive than Poly Identify redundant layout implementations Identify redundant layout implementations –Ex AOI: Y4, Y5 Dominant Process Effect COAO3BTC2NOR2XC_R2 -6 -4 -2 0 2 4 6 8 10 Process Corner Cell FR Improvement (ppb) orig Y1 Y2 Y3 Y4 Y5 Y6 Poly OpenPoly ShortM1 Open M1 Short NAND2 CELL Process Corner Poly OpenPoly ShortM1 Open M1 Short AOI CELL

18. Yield aware synthesys and place&route Proactive DFM Proactive DFM Maximize manufacturability by construction Maximize manufacturability by construction RTL Design Hierarchical Floorplan Physical Synthesis Chip Assembly Sign-off VERIFICATION Models Yield Gap Estimator Yield Optimizer Extended IP Yield Models Yield Estimation Yield Optimization DFM SW plug-ins Yield View (.pdfm) DFM LIBRARIES Standard Libraries

19. Conclusions Impact of design systematic and lithography yield loss mechanisms crossed over random phenomena Impact of design systematic and lithography yield loss mechanisms crossed over random phenomena Rule-based, reactive DFM is impractical Rule-based, reactive DFM is impractical Model-based, proactive DFM is the answer Model-based, proactive DFM is the answer –Early in the design flow –Find the best trade-off based on actual process capabilities –Before verification