1. MOS Field-Effect Transistors MOS Field-Effect Transistorsfor High-Speed Operation D.L. Pulfrey Department of Electrical and Computer Engineering University of British Columbia Vancouver, B.C. V6T1Z4, Canada pulfrey@ece.ubc.ca http://nano.ece.ubc.ca Day 4A, May 30, 2008, Pisa

2. Si MOSFET features 4 terminals 2D-device "The most abundant object made by mankind"

3. What happens ? NP-junctions and transistor action E B G S RBRB RjRj C ox C s =dQ s /dV aj HBT, BJT MOSFET x=0 D C

4. Transistor transfer characteristics MOSFET: S/B: 1E20/8E17 BJT: E/B: 1E19/1E17 V bi ONGetting HOT "OFF" Sub-threshold ON Note: relative "linearities" and current ranges

5. SUB-THRESHOLD CONDITION (DEPLETION) --- --- --- y x + ++ - -- V SB V GS - + iBiB ++ iGiG - + V DS Depletion layer forms

6. ON CONDITION (Strong Inversion) --- ------ V SB V GS - + iBiB iSiS iDiD iGiG + + + + + + + + - y Inversion layer forms V DS x

7. Decomposing the MOSFET Note: n + poly gate work functions oxide electron affinity and E g 1. Ignore S and D 2. Take vertical section from G → B y x y ECEC

8. Equilibrating the MOSCAP Equilibration process: - electrons transfer, driven by difference in E F - electrons recombine in body at the interface - depletion layer forms - charge separation creates field in oxide = -V fb

9. Surface potential and the PSP model qBqB

10. Introducing the channel potential THE GRADUAL CHANNEL APPROXIMATION

11. Implicit expression for  s

12. Varying degrees of inversion along the channel

13. The Drain Current Charge Sheet Approximation & Depletion Approximation DDE IEEE convention

14. Drain I-V characteristics Drain I-V characteristics Diffusion in sub-threshold Drift in strongly ON Smooth curves !

15. In Saturation: Q n (L) becomes very small. Field lines from gate terminate on acceptors in body. Drain end of channel is NOT in strong inversion, but SPICE models assume that it is ! Saturation and loss of inversion Saturation and loss of inversion

16. Development of SPICE Level 1 model Development of SPICE Level 1 model From PSP: Make strong- inversion assumptions Use Binomial Expansion Threshold voltage

17. Comparison of PSP and SPICE Comparison of PSP and SPICE V DS (V)

18. Improving the SPICE model Improving the SPICE model Increase  s at strong inversion

19. SPICE Level 49: allowing for v sat SPICE Level 49: allowing for v sat v =  E(x) v=v sat Combining the velocities: Putting this together with : GCA, CSM, dV CS (x)/dx

20. Comparison of SPICE Levels 1 and 49 Comparison of SPICE Levels 1 and 49

21. Subthreshold current Subthreshold current From PSP: Weak inversion: Expand Q n and substitute in PSP Diffusion Equation. Convert  s to V GS : Subthreshold current:

22. Subthreshold current comparison Subthreshold current comparison

23. Si CMOS: why is it dominant for digital? 4 reasons: 1. "Low" OFF current. 2.Compact logic: few transistors and no level shifting. 3.Small footprint. 4.Industrial investment. pFETnFET VSS VDD IN OUT Example of small footprint

24. CMOS: the Industrial drive Nodes relate to the DRAM half pitch, i.e., the width, and space in between, metal lines connecting DRAM bit cells

25. Logic speed is about Q and I Need: high  - certainly Low L - but it adversely affects V T High C ox - but low C ox ZL Low V DD - but it adversely affects I ON Low V T - but it adversely affects I SUBT

26. 3 major concerns for digital CMOS 3 major concerns for digital CMOS 1.Increasing I ON via mobility improvement 2.Reducing gate leakage via thicker, high-k dielectrics 3.Controlling V T and I subt via suppression of the short-channel effect

27. Improving  : direction-dependent m* k 1 is a direction k 2 and k 3 are orthogonal at the point of the energy minimum E C Which direction has the higher effective mass?

28. Conductivity effective mass m C * Electron accelerates in field E and reaches v d on next collision after time  v =0 v =v d  For unstrained Si: m C * = 0.26m 0 What happens when Si is biaxially tensioned?

29. Effect of biaxial tensile strain on E C  4 valleys raised in energy  2 valleys lowered in energy Unstrained

30. Strained Si at the 45nm node

31. High-k dielectrics High C OX needed for I D and S High t OX needed to reduce gate leakage Resolve conflict by increasing 

32. Tunneling through the oxide y (10 nm) Electron energy E Simplify the U profile → Solve SWE in each region: write as:

33. Solutions for   *   * ? What is   * ? Why is it : -oscillatory in the channel ? - damped in the oxide ? - constant in the gate ? Physically what is the "D-wave" ? y (m)

34. Transmission Probability: Definition 1. For the channel: 2. Do the derivatives and the conjugates: 3. Define the Transmission Probability: What do these mean ? What is the interpretation of this ?

35. Silica, hafnia, and electron affinity Silica, hafnia, and electron affinity

36. Tunneling current Tunneling current 100% improvement in C ox 50% improvement in C ox

37. The Short-Channel Effect The Short-Channel Effect  s = f (L, V DS )  V T = f (L, V DS )  s is determined by capacitive coupling via C ox and C body, AND by capacitive coupling via C DS

38. Reduce C DS by shrinking y j Reduce C DS by shrinking y j new y j It's like reducing the area of a parallel plate capacitor yjyj

39. SCE on Drain Current SCE on Drain Current L/y j (nm/nm) = 100/150 ---- 100/30 ---- 50/30 ---- 100/"0"

40. Reduce C DS by screening E x Reduce C DS by screening E x

41. Using SOI to beat SCE Using SOI to beat SCE Daryl Van Vorst Alvin Loke