1. A Timed-Automaton Based Method for Accurate Computation of Delay in the Presence of Cross-Talk Serdar Tasiran, Sunil P. Khatri, Sergio Yovine, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli Department of Electrical Engineering & Computer Sciences University of California, Berkeley

2. Overview Problem: Computing the delay of a combinational circuit. OUTLINE u Why a new method? u Timed automata s Input waveforms s Gate delay models s Cross-talk models u Computing delay with timed automata u How to fight computational complexity: s A conjunctively-decomposed representation s Conservative delay computation u Experimental results u Future research

3. Why a new method? l Before deep-submicron, a “solved problem” u Devadas, Keutzer, Malik ‘93 u McGeer, Saldanha, Brayton, Sangiovanni ‘’93 u Lam, Brayton ‘94 l Higher clock speeds u Fewer levels of logic u Greater timing accuracy required l Increased effect of parasitics: cross-talk (coupling) New process technologies, circuit families, dynamic logic, complex gates þConventional gate delay models no longer adequate þMust model new effects at circuit level þBoolean behavior and timing very interdependent þDelay depends on relative arrival times and values of inputs

4. What about topological analysis or simulation? l BUT: Number of possible input patterns exponential in # of inputs: l For large circuits, infeasible to simulate all patterns. l Delay not guaranteed unless all patterns are simulated. From ICCAD ‘97 tutorial on timing analysis. (Devgan, et. al.) l Topological delay does not account for cross-talk. l Assuming worst case cross-talk on all wires is too conservative. l Only transistor-level simulation provides desired accuracy

5. OUR APPROACH l Timed automata serve as delay models for circuit components l Delay parameters obtained by u Simulation u Analytical methods l Formal timing verification used to compute delay u All patterns covered; delay guaranteed. From ICCAD ‘97 tutorial on timing analysis. (Devgan, et. al.)

6. Timed Automata l Clocks (timers): real-valued variables, increase at same rate. l For each location u an output assignment u an invariant: a clock predicate. Clock predicate: Positive Boolean combination of x  d and x   d. i o 2  delay  3 i = 1, x  0 i =0, x  3 o = 0 2  x  3 x  3 o = 0 o = 1 Initial 2 3 i o reset x

7. Timed Automata as Delay Models l Example: NAND gate Determine delay parameters using SPICE simulation l Construct timed automaton model with these parameters. o =0 a = b = 0, x  0 o =0 o =1 x  d1 fall,max x  d2 fall,max o =0 x  d rise,max d2 fall,min  x d rise,min  x d1 fall,min  x a = 0, b =1 x  0 a = 1, b = 0 or a = b = 0 a b a b T1 T2 T3 T4 a b o

8. Timed Automata as Delay Models l Delay of this gate depends on u Old and new values of a, b, c, d, e u Relative arrival times of a, b, c, d, e l Modeling this circuit with [d min, d max ] is too coarse. l Delay models with state are more powerful l Timed automata can express sophisticated delay models l SPICE-simulate an individual circuit component exhaustively l Capture delay information into a timed automaton. l Desired amount of detail can be incorporated into delay model u Allows complexity-accuracy trade-off

9. Modeling Cross-talk WW S H T l As feature sizes shrink u Wire delays become dominant u W and S shrink linearly u T shrinks sub-linearly l Wire-to-wire capacitance becomes more significant. l Transitions on wires affect the delays of neighboring wires l Timed automaton model obtained by u Extraction of parasitics from layout u SPICE simulation for various input patterns l Simple cross-talk model u One wire switches u Wires switch in the same direction u Wires switch in the opposite direction stable x  0 one switch x  d one,max x  d opposite,max same x  d same,max x  0 opposite d one,min  x x  0 d same,min  x d opposite,min  x

10. Representing Sets of Input Waveforms l Two-vector delay: All inputs are initially stable and then switch simultaneously. clock = high i = i old i = i new For each input signal x  0 i = i old i = i new x = arrive i Different arrival times i = i old i = i new d min  x  d max Asynchronous input l Floating-mode: clock = high i = arbitrary i = i new For each input signal x  0

11. Delay Computation with Timed Automata GIVEN l Set of primary input waveforms. u Represented by timed automaton I. l A combinational circuit u Described as an interconnection of components G 1, G 2, …, G k MUST EXPLORE THE STATE SPACE OF l Automaton representing primary output waveforms  F = (  primary inputs, internal variables) ( I || G 1 || G 2 ||... || G k ) COMPUTE l Earliest and latest time each output of F changes its value

12. Exploiting the Structure of the Problem OBSERVATIONS: u State space has no cycles: otherwise circuit oscillates u Depth of state space limited by longest topological path: linear in circuit size l S (k) : Set of states that system can be in after k transitions. l Need to store S (k) only: Savings in space l May revisit states: Trading off time for memory l The representation for S (k) can be kept in conjunctively decomposed form. S (0) S (1) S (2) S (3) S (4) S (5)

13. Conjunctively Decomposed Representations 33 x3x3 22 x2x2 11 xixi 44 x4x4 Represent S (k) =  i  S i (k) where  S i (k) (  i, x i,  i-1, x i-1 ) represents (  i, x i ) as a function of (  i-1, x i-1 ) Compute S i (k,k+1) separately for each i, based on S i-1 (k,k+1) only: S i (k,k+1) = S i-1 (k,k+1)  S i (k)  T i l Support of each partition kept small: Smaller BDDs. MORE OBSERVATIONS: u Circuit components have bounded memory u State of component is correlated with components in its vicinity. Partition circuit into slices so that at step (k) possible values of (  i, x i ) determined uniquely by (  i-1, x i-1 )

14. Implementation l Timed-automaton-based delay computation algorithm implemented inside MOCHA. u BDD based implementation u Circuit is partitioned into slices u Decomposed representation of state sets u Reached state computation is performed on a per-partition basis. l Case study: n-bit carry skip adder

16. Case Study l Potential cross-talk l Doesn’t actually occur, because c_out and A3 are separated in time l Algorithm must be cross-talk aware not to overestimate delay

17. Experimental Results (1)

18. Experimental Results (2) l Compare: Monolithic representation can not complete the 4-bit example in 1GB.

19. Advantages of Approach l Modeling issues and verification and analysis issues are decoupled. l Timed automata serve as clean interface between the two. l The same algorithms remain applicable u For different delay models u At different levels of the hierarchy l Efficiency can be traded-off for accuracy without modifying analysis algorithm. l Exact characterization of delay computation problem u Allows sound conservative simplifications. l Timing properties other than delay can be verified u Hold and set-up times u For dynamic logic, is the input pulse wide enough to discharge output? u Is there a channel-connected path from supply to ground?

20. Status and Future Work l Timed-automaton-based delay computation algorithm implemented inside MOCHA. u BDD based implementation u Circuit is partitioned into slices u Decomposed representation of state sets u Reached state computation is performed on a per-partition basis. l Best performance so far: u 32-bit carry skip adder u 3 hours, ~80MB l FUTURE WORK: Exploit hierarchy