1. ISPD’2005, San Francisco April 5, 2005 Mapping Algorithm for Large-scale Field Programmable Analog Array (FPAA) Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson Hall, and David Anderson School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA 30332 {baskaya, sreddy, limsk, tyson, dva}@ece.gatech.edu

2. ISPD’2005, San Francisco April 5, 2005 2 Motivation: Gene’s law* Signal processing systems require low power Analog devices are preferred for low power operation * Gene Frantz, “Digital Signal Processor Trends”, IEEE Micro, Nov 2000 Power consumption trends in DSP microprocessors Contribution of analog design

3. ISPD’2005, San Francisco April 5, 2005 3 Field Programmable Analog Arrays (FPAA) Array of Computational Analog Blocks (CAB) Discrete time and continuous time versions Not LUT based => heterogeneous resources Interconnect lines not segmented => less routing options Device/interconnect constraints different from FPGA => existing methods do not easily apply!

4. ISPD’2005, San Francisco April 5, 2005 4 Previous Work Discrete Time (switched capacitor based) FPAA Former IMP EPAC: 150 kHz Former Motorola MPAA *: 200 kHz Continuous Time CMOS/Bipolar FPAA Lee-Gulak’1995: 125 kHz Fast Analog Solutions TRAC: 4 MHz Floating-gate based RASP: 11 MHz CAD tools Ganesan-Vemuri: DAC’2001 Wang-Vrudhula: Mixed Design of Integrated Circuits and Systems, 2001 *Now distributed by Anadigm

5. ISPD’2005, San Francisco April 5, 2005 5 Floating gate based FPAA V fg V tun Floating gate PFET switch Computational Analog Block (CAB) components 2D array of CABs

6. ISPD’2005, San Francisco April 5, 2005 6 Interconnect Analysis Three types of interconnects: type1: intra-CAB type2: inter-CAB, intra-column type3: inter-CAB, inter-column Clustering determines type1 vs. types 2&3 Clustering maximizes type1 use Vertical/horizontal wires are not segmented (unlike FPGA) R ~ 10 k  (switch on resistance) C x =  (all switch C’s on a line)

7. ISPD’2005, San Francisco April 5, 2005 7 Layout of a single CAB in FPAA components switch matrix

8. ISPD’2005, San Francisco April 5, 2005 8 Advantages of floating-gate based FPAA Larger scale More components per CAB More CABs per chip More component variety Floating gate PFET switch technology Non-volatile memory unit Programmable on resistance Linear Voltage-Current characteristics

9. ISPD’2005, San Francisco April 5, 2005 9 Analog Circuit Modeling *netlist description.device fpaa1.dev vcc 1 0 in1 2 0 in2 3 0 out1 4 0 out2 5 0 op1 2 6 7 cg1 6 0 nf1 3 10 0 cf1 10 11 mm2 11 12 13 vm1 8 9 12 13 x x x x 4 5 x x.l2constraints op1 ca1 cg1….end - + In1 max min In2 max min C 4 (SOS) InOut 4*4 Vector Multiplier Out2Out1 op1 mm1 cf1 nf1 mm2vm1 pf1 cg1 ca1 In2 Out1 Out2 In1 gnd vcc ps1 ps2 ps3 ps4 ps5 ps6 Extracting a directed graph from an analog circuit

10. ISPD’2005, San Francisco April 5, 2005 10 FPAA device modeling 8*8 FPAA and its graph based representation Small circles => routing switches Large circles => CABs

11. ISPD’2005, San Francisco April 5, 2005 11 Problem Formulation Objective Minimum number of CABs Minimum number of inter-CAB connections Constraints User constraints: certain components have to be in the same CAB Device constraints: each CAB can accommodate certain number of components of each type Net constraints: each CAB can have a maximum number of nets for intra-CAB and inter-CAB connections

12. ISPD’2005, San Francisco April 5, 2005 12 Overview of FPAA Clustering Simple (but effective) greedy heuristic 1.Pre-cluster user-defined components 2.Order circuit components 3.For each component in order 1.Find the best CAB 2.Merge the component & CAB 3.If no CAB available 1.allow constraint violation 2.fix it by adding more neighbors 4.Compute utilization

13. ISPD’2005, San Francisco April 5, 2005 13 FPAA Clustering Algorithm 1. Determine constrained groups 2. Modified Hyper Edge Coarsening (MHEC) ordering 3. Assign groups/components to the best available CABs i. High priority (scarce) components ii. User defined groups iii. Remaining components in MHEC ascending order pf1 cf1 nf1 mm1 CAB1 CAB2 CAB3CAB4 ps6 ps5 vm1 op1 cg1 ca1 mm2 CAB1CAB2 CAB3 CAB4 ps6 ps5 vm1 CAB1 CAB2 CAB3CAB4 ps6 ps5 vm1 op1 cg1 ca1

14. ISPD’2005, San Francisco April 5, 2005 14 How to select the best CAB? Check availability of the CAB Device constrains Net constraints If available, rank the CAB in favor of: Resulting CAB occupancy Net increase in intra-CAB connections Net decrease in inter-CAB connections Select CAB with highest rank

15. ISPD’2005, San Francisco April 5, 2005 15 Inter-CAB Interconnect Reduction If a component has too many connections to fit in “ANY” CAB: Select CAB with smallest violation Look for components to reduce inter-CAB interconnects pkey: number of nets NOT between component and CAB skey: number of nets between component and CAB Pick the lowest pkey & break ties with higher skey cutsize: before => 6 nets after => 5 nets

16. ISPD’2005, San Francisco April 5, 2005 16 Recent Progress FPAA clustering has been improved to include net- driven, path-driven and a hybrid of net/path-driven approaches Net-driven minimizes inter-CAB connections Path-driven considers path length balance FPAA Placement has been implemented

17. ISPD’2005, San Francisco April 5, 2005 17 Experimental Setup FPAA Architectures benchmarks  We cluster each circuit w/ four different cell ordering methods: random, net-driven, net-path driven & path-driven

18. ISPD’2005, San Francisco April 5, 2005 18 Results

19. ISPD’2005, San Francisco April 5, 2005 19 Conclusion We require low power reconfigurable analog devices for signal processing applications Floating gate based FPAA provides a large-scale solution We developed an algorithm for clustering targeting floating gate based FPAA

20. ISPD’2005, San Francisco April 5, 2005 20 Future Work Complete FPAA Physical Synthesis Tool including: Clustering Placement Routing Synthesize circuits => measurements Elaborate FPAA switch vs wire analysis Optimal FPAA Architecture Selection

21. ISPD’2005, San Francisco April 5, 2005 21 Thank you