1. THE ARITHMETIC-LOGIC UNIT

2. BINARY HALF-ADDER

3. BINARY HALF-ADDER condt Half adder InputOutput XYSC 0000 0110 1010 1101

4. Karnaugh Map and formulae for S 01 10

5. FULL ADDER InputsOutputs XYCiCi S C o 00000 00110 01010 01101 10010 10101 11001 11111

6. Karnaugh Map and formulae for S 0101 1010

7. Karnaugh Map and formulae for carry out 0010 0111

8. FULL ADDER condt Half adder 1 1 2 S2S2

9. FULL ADDER condt

10. FULL ADDER (IBM version)

11. FULL ADDER (IBM version) condt

12. PARALLEL ADDER

13. Applying the parallel adder for addition of natural numbers Examples a)b)

14. Applying the parallel adder for addition of integers in 2s complement code Examples a)

15. Example b) Skip!

16. Example c) Skip! Contradiction because

17. Applying the parallel adder for addition of integers in 1s complement code Example a)

18. Example b)

19. Parallel addition and subtraction

20. Basic logic operations

21. Shift operations

22. Generalized parallel arithmetic element

23. Problems encountered during multiplication Multiplicand Multiplier Partial products Product

24. Operations to be performed by ALU during multiplication: To sense whether a given bit is 1 or 0; To shift left partial products; To add the partial products.

25. Basic steps during multiplication: The accumulator is reset to 0, the multiplicand is load to the register Y and the multiplier is load to the register B. Accumulator 0………….0 B register multiplier Y register multiplicand

26. Basic steps during multiplication condt The following basic step is repeated n times where n is the number of bits in magnitude part of the numbers being multiplied: –1 0 If the rightmost bit in the B register is a 0, the combined accumulator and B register are shifted right one place. –2 0 If the rightmost bit in the B register is a 1, the number in Y register is added to the contents of the accumulator, and then the combined accumulator and B register are shifted right one place. When basic steps are finished, the contents of the combined accumulator and the B register consist of the product being derived. The sign of it is set by a separate circuit.

27. Example Product: 0001110101 2

28. Problems encountered during division Divisor Dividend Remainder Quotient a)

29. Problems encountered during division condt Remainder b) Dividend Divisor Quotient

30. Problems encountered during division condt Remainder c) Divisor Quotient Dividend

31. Description of the division procedure: Before the procedure starts, the B register is reset to 0, the dividend is read into the accumulator and the divisor into the Y register. After the division, the quotient is stored in the B register, and the remainder in the accumulator. Both divisor and dividend are to be positive. Accumulator dividend Y register divisor B register 00000

32. Description of the division procedure condt The procedure is divided into the following steps: –Step I. A „trial division” is made by subtracting the Y register from the accumulator. The sign bit of the accumulator is examined and the dividend (accumulator) is restored by adding the divisor to the result of the subtraction. If the above sign bit is 1, the process of division is completed, if it is 0, the process is continued.

33. Description of the division procedure condt –Step II. The leftmost 1 bit in the divisor is aligned with the leftmost 1 bit in the dividend by shifting the divisor left and recording the number of shifts required to make this alignment. That number of shifts plus 1 is the value of the parameter p applied in the next step. –Step III. The contents of the Y register is subtracted from the accumulator (operation performed in 2s complement code, the result replaces the contents of the accumulator). There are two possible cases. a) A new contents of the accumulator represents a negative number i.e. its sign bit is 1. Therefore the previous contents of the accumulator is restored by adding to it the contents of the Y register and the long register X+B is shifted left one place putting 0 is as the rightmost bit of X+B. b) A new contents of the accumulator represents a non negative number i.e. its sign bit is 0. In that case the long register X+B is shifted left one place putting 1 as the rightmost bit of X+B. The step III is repeated p times. –Step IV. The contents of the accumulator is shifted right p times.

34. Examples a)c) b)

35. Example a) quotient: 10 2 ; remainder: 0 2.

36. Example b) quotient: 0 2 ; remainder: 110 2.

37. Example c) quotient: 101 2 ; remainder: 1 2.