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TimePix / InGrid Problems and solutions Yevgen Bilevych Amsterdam 28.01.2013
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8’’ TimePix wafer 107 single chips Thickness 725 µm Surface materials: - Aluminum (aluminum oxide) - Silicon nitride - Silicon oxide
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TimePix chip 14111 m 16120 m 256 x 256 pixels 20 m 10 m CHIPEDGE Column 0 Column 1 Column 2Column 3Column 4 Column 251Column 252Column 253 Column 254Column 255 CHIPEDGE 55 m 20 m 28.3 m 48.22 m 57.7 m Pixel Row 255 Pixel Row 254 Pixel Row 253 Pixel Row 1 Pixel Row 0 Detector Guard Ring Row Snake Top Row Snake Bottom Row
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Main technological steps for the formation of structure TimePix / SU-8 / Al grid 4. Formation of structure “support” / grid 1. Formation of protection layer 2. Deposition of spacer material 3. Deposition of the Grid material
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Wafer surface quality inspection W0058 EW5MWBX
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Wafer surface quality inspection W0059 EU5MWDX
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Wafer surface quality inspection W0060 E85MWZX
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Wafer surface quality inspection W0061 E15MVPX
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Polyimide mask Microsystems HD 4100 polyimide - negative tone, solvent developed, photodefinable polyimide Steps: Spinning Baking Exposition Development Silicon nitride deposition Chemical activation of polyimide Stripping Advantage: Silicon technology compatible Perfect alignment No residuals Disadvantage: Temperature sensitive process Time consuming process mechanical scratching of bonding pads
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Oxford 80 (PECVD) PECVD Plasma enhanced chemical vapor deposition Silicone oxide or silicone nitride formation Plasma power max 600 W at 187.5 kHz, max 300 W at 13.56 MHz plasma frequency Substrate temperature 100 up to 400 °C Layers contain hydrogen
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just deposited Si x N y “chemically activated polyimide”
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- C - O Bisphenol A Novolak epoxy oligomer SU-8 photoresist composition : - Gamma Butyrolactone 22-60% - Up to 10 % Triarylsulfonium / Hexafluoroantimonate Salt (3.3% for SU-8/50) - Propylene Carbonate 1-5% - Epoxy Resin 35-75% SU-8 - epoxy-based negative photoresist R1 O CHCH 2 + H + R1 OH CH CH 2 + + R1 O CHCH 2 - H + R1 O CH CH 2 R1 O CH CH 2 SU-8 crosslinking mechanism
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SU-8 layer map
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Al layer Sputtering system Leybold Z660 12345678910111213141516171819202122232425 xxxxxxxxxxxxxxxxxxxxxx DC 50%, no sputter etching, 30 sec – the deposition time for every sputtering run, + cooling delay Total thickness: ~ 800 nm
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deposition of Al layer Chip SU-8 photoresist aluminum SU-8 column protection layer Chip Pixel pad Cross-linked SU-8 photoresist
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Development of SU-8 1.Acetone 2.Acetone:IPA:H 2 O (1:1:2) 3.Acetone:IPA:H 2 O (1:1:1) 4.Acetone:IPA (1:1) 5.Microstrip 6001 6.H 2 O 7.IPA 8. Acetone 9.Drying in the air
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Standard development
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Extra cleaning
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O 2 plasma cleaning
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O 2 plasma cleaning (long time)
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IZM-5 started: W0062 (4 m Si x N y ) and W0063 (8 m Si x N y ) Modified InGrid (mInGrid) - started Summary W0058 EW5MWBX () in process W0058 EW5MWBX (4 m Si x N y ) in process W0059 () broken W0059 EU5MWDX (4 m Si x N y ) broken W0060 E85MWZX () in process W0060 E85MWZX (8 m Si x N y ) in process W0061 E15MVPX ()cleaning W0061 E15MVPX (8 m Si x N y ) requires the cleaning
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