1. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 1 Tutorial on Chemical Mechanical Polishing (CMP) Ara Philipossian Intel Corporation  1999 Arizona Board of Regents for The University of Arizona

2. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 2 Outline of the Tutorial Section A:Overview –Generalized schematics of CMP and Post-CMP Clean –Current CMP environment –Evolution of CMP –The CMP Module –The CMP Infrastructure Section B: Polishing equipment trends Section C: Polishing process issues Section D: Consumables (pads & slurries) –Quality issues –Factors affecting productivity –Critical pad and slurry parameters

3. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 3 Outline of the Tutorial Section E: Industry - University Gaps Section F: Environmental Health and Safety (EHS) considerations Section G: Slurry fluid dynamics Section H: Slurry re-use Section I: Post-CMP cleaning

4. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 4 Section A: Overview

5. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 5 Schematic Diagram of Chemical Mechanical Polishing Process Carrier Retaining Ring Slurry Polish Platen Pad Pad Conditioner Downforce

6. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 6 Schematic Diagram of Post-CMP Scrubbing wafer PVA brush Cleaning Fluid

7. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 7 CMP Environment CMP has become the widely accepted planarization method of choice for < 0.5 micron technologies The overall CMP market is growing at a rate of ~ 50% per year The current momentum in process integration and scaling far exceeds the fundamental understanding of complex interactions among: –Equipment –Consumables (i.e. slurry, pad, carrier film) –Process parameters –IC type and density Processes and consumables are formulated to provide optimum performance for a given equipment and IC product set For a 4 metal layer process with STI, ILD and W CMP steps, approximately 20 polishers are needed ( 60% utilization, 20 wafers per hour, 5000 wafer starts per week factory)

8. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 8 CMP Environment Protection of intellectual property hinders shared learning among IC, equipment and consumables manufacturers, but also provides a technological advantage: –Internally developed equipment, precision parts and sub-systems Morimoto & Patterson, US Patent No. 5,104,828 (1992) Breivogel, Blanchard & Prince, US Patent No. 5,216,843 (1993) Breivogel, Louke, Oliver, Yau & Barns, US Patent No. 5,554,064 (1996) –Internal slurry formulations licensed to suppliers for exclusive use –Customized pads –3rd party modifications of off-the-shelf consumables and equipment

9. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 9 Evolution of CMP

10. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 10 Evolution of CMP

11. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 11 a - Negotiate Price b - Insert competition c - Reduce disposal volume d - reclaim and re-use a - Negotiate Price b - Insert competition c - Increase pad life via better QC d - Increase pad life via better chemistry Total Cost Chemical Expenditure per fully Processed Product Wafer (Disposal and Treatments Costs are Included)

12. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 12 The CMP Module Polish In-Situ Measure Measure & Inspect Re-work Product and Test Wafers Water Slurry Pad Energy Clean Product and Test Wafers Liquid Waste Energy Filter Solid Waste Carrier Film

13. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 13 Polishing: Rotary (single or multiple heads and platens) –Orbital (single or multiple heads and platens) –Linear (multiple heads) Cleaning: Mechanical scrubbing (with & without chemistry or megasonics) Wet cleaning (with and without megasonics) Measurement and inspection: Removal Rate –Thickness uniformity (wafer-to-wafer, within-die, die-to-die) –Defect density –Dishing –Erosion –Plug recess Planarity –Surface Roughness The CMP Infrastructure

14. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 14 In-situ Measurement: –End-point detection Consumables: Pad (polyurethane, impregnated felt, fixed abrasive) Slurry (silica, alumina or ceria abrasives, organic and inorganic additives) –Filter (point-of-use or post-slurry-blending) –Conditioning (diamonds) Slurry delivery Water delivery Waste treatment: –Off-site disposal –Recycling Re-use The CMP Infrastructure

15. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 15 Section B: Polishing Equipment Trends Philipossian, Morimoto and Cadien, CMP-MIC, Santa Clara, CA (1996)

16. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 16 Equipment Environment In high-volume manufacturing, the balance between high throughput, size and complexity needs to be maintained

17. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 17 Equipment Environment Development of automated dry-in-dry-out systems that: Improve throughput Reduce footprint Reduce total cost Reduce ergonomic issues Reduce number of people Robot CleanI/O Polish 1Polish 2 Polish I/O Clean Ability to polish 300-mm wafers In-situ metrology for device wafers with closed-loop control

18. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 18 Section C: Polishing Process Issues Philipossian, Morimoto and Cadien, CMP-MIC, Santa Clara, CA (1996)

19. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 19 Process Issues Within-Wafer Non-Uniformity (WIWNU): –Wafer flatness –Carrier film, pad & slurry type (discussed earlier) –Carrier design –Pad conditioning method –Platen & carrier speeds –Retaining ring design (i.e. extent of pressure discontinuity between wafer edge and retaining ring) –Slurry injection scheme Defect density: – Pad & slurry type – Use of secondary platen – Post-CMP cleaning method Removal rate: – Carrier film, pad & slurry type (discussed earlier) – Downforce – Platen & carrier speeds

20. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 20 Process Issues Planarity: –Pad type –Circuit density & structure size –Extent of ILD removed –Downforce, platen speed & carrier speeds –Step Height Ratio (SHR) = Post Step Height / Pre Step Height –The goal is to minimize SHR and maximize PD thereby minimizing Within-Die Non-Uniformity (WIDNU) Planarization Distance (PD) Post Pre Polish

21. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 21 Effect of Structure Size & Density on Post Step Height SHR is greater on metal pads compared to isolated narrow lines Areas with lower circuit density polish faster than areas with dense underlying topography Each circuit design will have a different WIDNU due to variations in size and density of interconnects

22. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 22 Effect of Downforce on Removal Rate & Planarity Increase in downforce (wafer pressure applied to the polishing pad) results in a linear increase in removal rate (i.e. Preston’s Equation) Increase in downforce degrades planarity due to pad deformation and subsequent increase in local pressure at the ‘valley’ regions (i.e. Hook’s Law)

23. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 23 Effect of Platen Speed on Removal Rate & Planarity Increase in platen speed increases removal rate linearly (i.e. Preston’s Equation) Increase in platen speed improves planarity At higher speeds the pad contacts mainly the ‘hill’ regions since it does not have sufficient time to conform to the ‘valley’ regions

24. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 24 Effect of Carrier Speed on Wafer Center & Edge Removal Rates Platen speed is maintained at 70 RPM Center-to-edge removal rate difference increases with increasing carrier speed Carrier diameter << platen diameter & at low carrier speeds, the linear velocity vector created by the carrier is much smaller than that created by the platen As carrier speeds approach & exceed platen speed, the linear velocity vector created by the carrier becomes significant Edge Center

25. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 25 Effect of Pad Hardness on Post Step Height and Planarization Distance Harder pads deform less under pressure thus leading to: - Lower SHR, higher PD, and improved WIDNU (i.e in mm range) - Poorer WIWNU (i.e. in cm range) Harder pads also result in higher removal rates and higher defect densities Soft Pad Hard Pad

26. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 26 Effect of Pad Compressibility on Electrical Integrity of ILD Kaufman, Proceedings of Spring MRS, CA (1995)

27. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 27 Section D: CMP Consumables Philipossian, Sanaulla, and Moinpour, Semicon West Technical Session on CMP, CA (1998)

28. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 28 CMP Slurries and Pads Areas of Concern Availability Design EHS Legal Supplier Quality & Reliability Manufacturability Total Cost

29. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 29 Quality Issues Intel Corporation All Chemicals

30. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 30 Quality Issues Intel Corporation CMP Slurries 70% Abrasive Issues 20% Foreign Matter 10% Other

31. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 31 Quality Issues Intel Corporation CMP Pads 40% Texture 30% Foreign Matter 20% Adhesive 10% Other

32. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 32 Impact of Quality Issues The Quality Indicator (QI) QI = 100 - (2) [(a) + (2) (b) + (4) (c) + (8) (d) + (16) (e)] SCAR:Supplier Corrective Action Request Note:The Quality Indicator is measured on a quarterly basis for each supplier e = No. of factory interrupts (i.e. issues resulting in tool or factory downtime, or product loss) d = No. of near misses (i.e. issues requiring extra Intel resources to keep the factory running) c = No. of repeat SCARs b = No. of SCARs (i.e. issues caused by gross supplier negligence) a = No. of issues (i.e. all issues regardless of impact to Intel)

33. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 33 Supplier Comparison CMP Suppliers vs. Photoresist and Wet Chemical Suppliers (Data Collected Since 1Q96) Challenge

34. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 34 Equipment - Availability - Reliability - Integrated Run Rate Productivity Factors Influencing Productivity Labor - EHS - Ergonomics - Automation Process Stability & Manufacturability - RR - WIWNU, WTWNU, WIDNU - Defects - Planarity - Pad life - Pad & slurry quality

35. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 35 Tool Integration and Automation Integrated Run Rate Robot R1 CMP#1 R2 CMP#2 R3 Cleaner R4 Robot R1 Wafers Robot R1 R5 CleanerRobot R1 CMP#3 CMP#1 R2 CMP#2 R3 R4 Wafers Robot Limited Cleaner Limited

36. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 36 Changing pads in high-volume manufacturing poses a serious ergonomic issue: –Frequency of change –Difficulty of change A compromise must be reached between adhesive strength and its effect on the polishing process: –Hardness –Compressibility –Corrosion resistance –Use of chemicals to remove adhesive residues Mechanical pad-pullers are becoming a requirement in factories Polishing Pad Life Frequency of Changing Pads as a Function of Pad Life

37. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 37 Polishing Pad Life Effect of Pad Life on Tool Availability Availability (%) = 100 - Scheduled Downtime - Unscheduled Downtime Scheduled Downtime: –Tool PM, facilities PM, monitors, tool qualification and consumables changeout Unscheduled Downtime: –Out-of-control conditions, repairs

38. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 38 5000 WSPW 5 oxide polish steps Pad life of 500 (i.e. number of wafers polished before pad change) Pad change duration: –Complexity of process qualification on fresh pad (i.e. pad break-in) –Other consumable changes (i.e. wafer carrier & pad conditioner) –Ergonomics of pad change (i.e. pad size and adhesive strength) No. of Polishers vs. Tool Availability Effect of Pad Change Duration (Pad Life & Scheduled and Unscheduled Downtime are Fixed)

39. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 39 No. of Polishers vs. Tool Availability Effect of Un-Scheduled Downtime (Pad Life, Pad Change Duration and Scheduled Downtime are Fixed)

40. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 40 Oxide Polisher Downtime Pareto Chart C+P C+P+T C+P C = Consumables P = Process T = Tool

41. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 41 Oxide Polisher Downtime Pareto Chart average pad life average POU filter life variability in pad and slurry properties (PSD) average filter life variability in slurry properties (PSD)

42. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 42 Effect of pH and Abrasive Content on ILD Removal Rate Scherber et al., Proceedings of the Symposium on Planarization Technology: CMP, Semicon West (1994)

43. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 43 Effect of Trace Metals on ILD Polish Performance -All units in ppm -Slurries F & G are identical except for the metal content -Comparable removal rate and uniformity

44. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 44 Effect of Hydrocarbons on ILD Polish Performance - Slurries H & I are identical except for the hydrocarbon content -Hydrocarbon contained a polar group -Comparable removal rate and uniformity -Majority of defects were ‘scratches’

45. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 45 Abrasive Geometry Primary Particle Aggregate

46. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 46 Effect of Abrasive Geometry on ILD Polish Performance - Fumed silica abrasive -Constant pH and abrasive content - Comparable defect density and planarity

47. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 47 Effect of Abrasive Geometry on ILD Removal Rate

48. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 48 Section E: Industry - University Gaps

49. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 49 Development of Core Competencies (Industry - University Gaps)

50. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 50 Development of Core Competencies (Industry - University Gaps)

51. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 51 Section F: EHS Hierarchy and Considerations Philipossian, Moinpour and Poliak, Proceedings of VMIC, Santa Clara, CA (1998)

52. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 52 EHS Hierarchy & Issues Environmental regulations are growing at an amazing rate: –Federal and local initiatives & regulations –International initiatives Recycling regulations are extremely complex and require detailed understanding and follow-through Many new materials are not designed with EHS in mind. In many cases, suppliers do not even know the potential EHS impact of these materials To find out late in the process that a material has a serious EHS impact can delay technology introduction or increase cost Most chemical suppliers have committed to ownership from cradle- to-grave, but follow-through is poor Replace > Reduce > Re-use > Recycle > Abate

53. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 53 Growth of US Environmental Legislation (Cumulative No. of Environmental Laws) Technology & Environment, Washington DC, National Academy Press, p. 101 (1989)

54. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 54 EHS in CMP (Level - I Considerations) energy inputs chemical inputs EHS ergonomics chemical outputs energy outputs

55. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 55 energy inputs chemical inputs ergonomics chemical outputs polish tool post-polish tool film type IC type slurry type process recipe pad type post-polish consumable IC density wafer size publicly owned treatment works in-fab discharge treatment method fab location wafer starts per week energy outputs chemical blending & delivery system UPW system EHS EHS in CMP (Level - II Considerations)

56. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 56 energy inputs chemical inputs ergonomics chemical outputs polish tool post-polish tool film type IC type slurry type process recipe pad type post-polish consumable IC density wafer size publicly owned treatment works in-fab discharge treatment method fab location wafer starts per week energy outputs chemical blending & delivery system UPW system pH abrasive type abrasive size abrasive shape abr. morphology solids content oxidizer type additive type buffer type base type acid type zeta potential ionic strength viscosity color shelf life pot life dispersability EHS in CMP (Level - III Considerations)

57. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 57 energy inputs chemical inputs ergonomics chemical outputs polish tool post-polish tool film type IC type slurry type process recipe pad type post-polish consumable IC density wafer size publicly owned treatment works in-fab discharge treatment method fab location wafer starts per week energy outputs chemical blending & delivery system UPW system size material stack thickness texture morphology hardness specific gravity compressibility hole pattern groove pattern adhesive strength life shelf life EHS in CMP (Level - III Considerations)

58. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 58 energy inputs chemical inputs ergonomics chemical outputs polish tool post-polish tool film type IC type slurry type process recipe pad type post-polish consumable IC density wafer size publicly owned treatment works in-fab discharge treatment method fab location wafer starts per week energy outputs chemical blending & delivery system UPW system automation footprint conditioner endpoint detection water inj. scheme slurry inj. scheme effluent segregation POU filtration flow dynamics re-use compatibility carrier design platen design ring design number of platens rotation scheme vent design parts clean req. PPE req. ease of maint. run rate EHS in CMP (Level - III Considerations)

59. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 59 energy inputs chemical inputs ergonomics chemical outputs polish tool post-polish tool film type IC type slurry type process recipe pad type post-polish consumable IC density wafer size publicly owned treatment works in-fab discharge treatment method fab location wafer starts per week energy outputs chemical blending & delivery system UPW system water flow rate slurry flow rate chemical flow rate dilution flow overlap automation carrier speed platen speed down-force back-pressure number of platens conditioning recipe EHS in CMP (Level - III Considerations)

60. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 60 Section G: CMP Fluid Dynamics Coppeta, Roger, Racz, Kaufman & Philipossian, Pad effects on slurry transport beneath a wafer during polishing, CMP-MIC, Santa Clara (1998)

61. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 61 Fluid Dynamics Goal: –Reduce slurry dispense volume –Increase slurry utilization efficiency –Entrain a uniform layer of new slurry beneath the wafer –Prevent polished material from being re-entrained beneath the wafer Key issues which need to be comprehended: –Chemical & mechanical factors which influence polishing –Slurry film thickness between wafer and the pad –Slurry transport mechanism, and factors that influence slurry transport Slurry injection scheme Slurry flow rate Pad type, conditioning and topography Platen and carrier speed

62. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 62 Dual-Emission Laser-Induced Fluorescence Glass Wafer Polish Platen Pad Camera Laser Slurry with Fluorescence dyeSlurry

63. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 63 http:\\www.tuftl.tufts.edu

64. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 64 Slurry Transport Interrogation Region Wafer Post Examining: - Mean slurry age - Residence time - Slurry Gradients (flat pads) - Drag on wafer - Fluid thickness measurements Pad

65. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 65 Slurry Flow Rate Flat Pad Grooved Pad Manufacturer: Rodel Slurry Flow Rate: x cc/min Wafer Down Force: 4 psi Platen Speed: 60 rpm X-Y Groove Depth: 20 mils Time (sec) Percent New Slurry

66. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 66 Platen Speed Manufacturer: Freudenberg Slurry Flow Rate: 35 cc/min Wafer Down Force: 4 psi Platen Speed: x rpm X-Y Groove Depth: 20 mils Flat Pad Grooved Pad Time (sec) Percent New Slurry

67. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 67 Static Case Pad deformation: (4 psi, 0 rpm) Image of a single pad Thickness profile as determined by ratiometric technique

68. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 68 Section H: Slurry Reuse Kodama, A reclaim use of CMP slurry, 29th Symposium on ULSI Ultra Clean Technology, Tokyo, Japan (1996)

69. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 69 Slurry Re-Use Experimental Setup Secondary Platen Primary Platen Slurry Capture Tub Spent Slurry Reservoir Pump & Filter

70. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 70 RR & WIWNU vs. Slurry Reclaim fumed 50 / 200 nm colloidal 102 / 212 nm

71. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 71 Surface Roughness & pH vs. Slurry Reclaim fumed 50 / 200 nm colloidal 102 / 212 nm

72. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 72 Mean Aggregate Size vs. Slurry Reclaim fumed 50 / 200 nm colloidal 102 / 212 nm

73. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 73 Section I: Post-CMP Cleaning Moinpour & Burke, Keynote Address, CMP-MIC, Santa Clara (1998) Jankovsky, 3rd CMP Workshop, Lake Placid, NY (1998) Busnaina, 3rd CMP Workshop, Lake Placid, NY (1998)

74. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 74 Post-CMP Clean Defects & Contamination: –Abrasive particle residues (i.e. silica, alumina or ceria) –Chemicals on surface (i.e. surfactants, or slurry additives) –Alkali metal contaminants (i.e. K or Na) –Heavy metals (i.e. Fe) –Pad residues –Pad conditioner (i.e. diamond) residues Requirements: –Quick and repeatable –Cause do damage to devices or films (i.e. change roughness or planarity) –No residue or redeposition –Low cost of ownership (COO) Environment: –Mechanical scrubbing (with & without chemistry or megasonics) –Wet cleaning (with and without megasonics)

75. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 75 Post-CMP Clean (Defect Reduction Strategies) Step - I … Reduce defects during the CMP process: –Use slurry additives Step - II … Reduce defects further by performing an additional buffing process: –Use chemicals on the secondary platen Step - III … Reduce defects even further during the post- CMP cleaning process: –Use chemicals in the post- CMP cleaning tool

76. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 76 Post-CMP Clean (A Sampling of Chemicals or Methods Cited in the Literature)

77. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 77 0.35 um, 200mm technology Effect of post ILD CMP clean chemistry on end-of-line yield Process 1 and Process 2 are identical polish processes Process 2 uses a different Post-CMP Clean chemistry Improved consumable lifetime No impact on overall run rate Post-CMP Clean (Process Improvement)

78. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 78 Cleaning Theory Particles in liquids: –Primary cause of adhesion is van der Walls forces (DLVO Theory) –Secondary cause of adhesion is Electric Double Layer (EDL) forces (however, they are usually repulsive and can help in particle removal) Particles in solution become charged Stern Layer + Diffuse Layer = EDL Potential at shear plane = Zeta Potential EDL thickness varies as inverse square root of the ionic strength (i.e. 4X increase in ionic strength will reduce EDL thickness by 2X) EDL and the Zeta Potential are a function of pH

79. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 79 Cleaning Theory ELECTRIC DOUBLE LAYER

80. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 80 Cleaning Theory DLVO THEORY

81. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 81 Post-CMP Cleaning

82. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 82 Brush Cleaning Advantages: –Most common cleaning methodology –Double-side and edge cleaning capability –High energy scrub capability –The contact mechanism can help clean wafers with topography –Simple integration with dry- in-dry-out processing –Compatible with wet chemistry –Compatible with the recent advances in ‘smart-brushes’ (zeta-potential engineering) Disadvantages: –Contact with wafers may be harmful –Brush loading with particle and re-deposition –Low throughput –High COO (chemicals, DI water, consumables parts) –Static build-up which may increase particle adhesion forces –Tough for brushes to contact high aspect ratio topography –Brush shedding –Brush break-in required

83. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Philipossian 83 Wet Chemical Cleaning Advantages: –More chemically intensive compared to brush cleaning –Residues and foreign matter can be readily dissolved and removed from the surface –Ability to manipulate zeta potential to remove particles –Low COO –High throughput –Controlled cavitation (formation of gas bubbles by ultrasound) and acoustic streaming (steady flow induced by sound field) can be used to detach and remove particles from the surface –Formation of acoustic boundary layer Disadvantages: –Particle saturation in the recirculating tank –Difficult to integrate with dry-in-dry-out processing –Cleaning process must be tailored to each device layer and material –Uncontrolled cavitation may cause wafer surface damage