1. 1 A 90nm 512Mb 166MHz Multilevel Cell Flash Memory with 1.5MByte/s Programming Adopted from ISSCC Dig. Tech. Papers, Feb.2005, Intel Corporation[2.6] Presented By: Nadereh Hatami Class Presentation Advanced VLSI Design Course

2. 2 Outline Floating Gates introduction Multilevel Flash Cell Approach Device Information Multilevel Cell Sense Budget Stepped Gate (SG) Sensing Negative Deselected Row (NDR) Customer Selectable Output Drive Technology Conclusions

3. 3 A Typical Flash Memory Cell Adopted From [2]

4. 4 2-Bit Intel MLC Digital Code Assignment Digital CodeCharge Level 00Level 3 01Level 2 10Level 1 11Level 0

5. 5 Device Information  512Mb (8 partitions, 64Mb each) 256 independently erasable blocks  Object/Control Mode Programming  65ns Asynchronous mode access  Synchronous Burst 166MHz zero wait state 8W / 16W / Continuous Burst Modes Selectable Output Strength  Low Power Operation Deep Power-Down Mode (5uA) 1.7 – 2.0V core power supply (VCC) 1.35V – 2.0V output driver power supply (VCCQ)

6. 6 Multilevel Cell Sense Budget R1 Read Reference Level 3 (R3) Erase Verify (EV) PV1 R2 PV2 Program Verify Level 3 (PV3) Max V T limited by Cell and Program Placement Performance Min V T limited by Column Leakage Impact on Erase Increasing V T (~3V between R1 and R3) Some sense budget components Floating Gate (FG) to FG Coupling Apparent V T Change due to ΔV S V T Margin Required for Sensing Program State Width Post Retention Bake Erase State Width Post Retention Bake L0 L1 L2 L3 Count From [1]

7. 7 Floating Gate (FG) to FG Coupling Drain Shields Poly 1 FG-FG CouplingFG Coupling

8. 8 Apparent V T Change due to ΔV S Cell A = L1Cell B = L0 Cell A = L1Cell B = L3 From [1]  128 Cells Read in Parallel  1st Program Operation Places Cell A = L1  2 nd Program Operation Places Cell B = L3  Source Voltage Lowers for Cell A during L1 sense  Result: Lower Apparent V T

9. 9 Minimizing FG-FG Coupling & ΔV S Programming cells in an 8Kbit region in a single program operation:  Eliminates impact of Apparent ΔVT due to ΔVS  Minimizes impact of FG-FG Coupling

10. 10 Stepped Gate (SG) vs. Constant Gate (CG) Sensing R 3 R 2 R 1 CG Sensing Voltage Gate voltage varies for SG sensing 12 V GS I DS 3 Ref cell current varies depending on V T for CG sensing  SG Sensing uses a fixed reference current  CG Sensing uses a fixed gate voltage Ref cell current is constant for SG sensing From [1]

11. 11 Stepped Gate Sensing Scheme Concept From [1]

12. 12 Stepped Gate Sensing From [1]

13. 13 Negative Deselected Row (NDR) I REF - V T Cell w/ -V T Swamps Comparator Comp Erase V T Distribution Over-eased Cells Under- erased Cells V EV 0V w/o NDR w/ NDR From [1]

14. 14 Multilevel Cell Sense Margin Improvement Increasing V T (~3V between R1 and R3) Some sense margin components Sense Margin Improvement Floating Gate (FG) to FG Coupling VT Margin Required for Sensing Program State Width Post Retention Bake Erase State Width Post Retention Bake Result of Sense Margin Improvements  Can allow wider V T distribution to achieve faster program performance.  Can widen budget by lowering EV because Min V T is not limited by Column Leakage Impact on Erase. R1 R3 EV PV1 R2 PV2 PV3 L0 L1 L2 L3 Count From [1]

15. 15 Customer Selectable Output Drive From [1] Customer Selectable Output Drive Strength for matching system load

16. 16 Die Photo Prog Control Circuits One Block ½ Partition X-Decoder Y-Select Sensing / Bitline Sel Die Size = 42.5mm 2 From [1]

17. 17 Technology Triple Well 90nm CMOS 3 Cu Interconnect Layers Dual Poly Layers, Co-Salicide Flash Cell Effective Bit Size 0.038μm2 Tunnel Oxide Thickness 88Å Interpoly Dielectric Thickness 140Å Periphery Transistor Oxide Thickness 150Å High Voltage 45Å Low Voltage

18. 18 Conclusions Significant Sense Budget Consumers FG-FG Coupling Apparent VT change due to change in data pattern storage Apparent VT change due to temperature change between cell placement verify and read. Design Techniques that Improve Budget 2-row programming SG sensing NDR Combining 90nm CMOS technology with multilevel cell Flash and the design techniques that have been presented delivers world-class performance of: 166MHz Synchronous Burst Read 1.5 MByte/s Program

19. 19 References [1] Intel, Folsom, CA, “A 90nm 512Mb 166Mhz Multilevel Cell Flash Memory With 1.5MB/s Programming”, ISSCC Dig. Tech. Papers, Feb. 2005 [2] Bauer, M. et al., “A Multilevel-cell 32Mb Flash Memory,” ISSCC Dig. Tech. Papers, pp.132-133, Feb., 1995. [3] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic,” Digital Integrated Circuits, A Design Perspective,2th edition”, Book Slides. [4] ISSCC Press Kit 2005 [5] http://www.siliconfareast.com/flash-memory.htmhttp://www.siliconfareast.com/flash-memory.htm [6] http://www.intel.comhttp://www.intel.com