1. Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng 1 Ion I. Mandoiu 2 Qinke Wang 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department, University of California at San Diego (2) CSE Department, University of Connecticut (3) CS Department, Georgia State University

2. Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

3. Mask and Wafer Cost Mask cost: $1M for 90 nm technology Wafer cost: $4K per wafer

4. Introduction to Multi-Project Wafer Share rising costs of mask tooling between multiple prototype and low production volume designs  Multi-Project Wafer Image courtesy of CMP and EuroPractice

5. History of Multi-Project Wafer Introduced in late 1970s and early 1980s Companies: MOSIS, CMP, TSMC Several approaches proposed Chen et al. give bottom-left fill algorithm, 2003 Anderson et al. proposed grid packing algorithm, 2003 Tools: MaskCompose, GTMuch

6. Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

7. Design Flow  Unique designs

8. Design Flow  Custom designs  Partition between reticles

9. Design Flow  Custom designs  Partition between shuttles  Reticle placement

10. Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map print shot-map

11. Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map  Dicing plan design

12. Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map  Dicing plan design

13. Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map  Dicing plan design  Extract dice

14. Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

15. Why Dicing a Problem? Sliced out A die is sliced out if and only if: - Four edges are on the cut lines - No cut lines pass through the die Dicing is easy for standard wafers. All dice will be sliced out. Dicing is complex for MPW. Most dice will be destroyed if placement is not well aligned. Side-to-side dicing is the prevalent wafer dicing technology

16. Side-to-side Dicing Problem Given: reticle placement wafer shot-map required volume for each die Find: Set of horizontal and vertical cut lines (dicing plan) To Minimize: w = # wafers used

17. H-Conflict dice are in H-Conflict if they can not be sliced out horizontally. 1 2 43 1 and 2 are in H-conflict Die 1 is in H-Conflict with entire row of Die 2. 1 2 43 1 2 43 1 2 43

18. Horizontal Dicing Plan A horizontal Dicing Plan (DP) is a set of lines which dice one row of prints A set of dice which are pairwise not in H-conflict can be sliced out by a DP We seek such maximal horizontal independent sets MHIS (MVIS) = set of all horizontal (vertical) DPs The dicing plan which slices out dice 1 and 4 1 2 4 3 1 2 4 3 1 2 4 3

19. Interval Coloring Two dice are in H-conflict iff their vertical projections overlap  Interval graph, which can be optimally colored All dice of the same color can be horizontally sliced out 1 2 4 3 1 2 4 3 1 2 4 3 1 2 4 3 12 34

20. Non-Linear Programming Formulation Assume the wafer is a rectangular array of prints. f H = # rows (with DP H) one DP per row = # rows whose dicing plans slice out D i

21. Non-Linear Programming Formulation Assume the wafer is a rectangular array of prints. g V = # columns (with DP V) = # columns whose dicing plans slice out D i one DP per column

22. Non-Linear Programming Formulation N(D i )= # required copies of die D i z=1/(# wafer) copies sliced out Must slice out at least the required volume

23. Non-Linear Programming Formulation Assume the wafer is a rectangular array of prints. f H = # rows (with DP H) g V = # columns (with DP V) N(D i )= # required copies of die D i Maximize: z = 1/(# wafers) Subject to:

24. Integer Linear Programming Formulation One DP per row

25. Integer Linear Programming Formulation One DP per column

26. Integer Linear Programming Formulation The print at r th row and c th column is diced by DP H and V iff we use H at the r th row and V at the c th column

27. Integer Linear Programming Formulation D i sliced out otherwise Sliced out at least required volume

28. Integer Linear Programming Formulation Maximize: z = 1/(# wafers) Subject to:

29. Iterative Augment and Search Algorithm (IASA) Choose initial dicing plan using interval graph coloring DP 1 DP 2

30. Iterative Augment and Search Algorithm (IASA) Choose initial dicing plan using interval graph coloring In each iteration, first check whether z will increase by changing the dicing plan for one row or column DP 1,…,DP |MVIS| DP 1 DP 2 DP 1,…,DP |MHIS|

31. Iterative Augment and Search Algorithm (IASA) Choose initial dicing plan using interval graph coloring In each iteration, first check whether z will increase by changing the dicing plan for one row or column DP 1 DP 2 DP 1,…,DP |MHIS| Choose one dicing plan for one new row or column which maximizes z DP 3

32. Experiment Setup Ten random testcases with different numbers of dice Required production volume is 40 for all dice Assume a wafer has 10 rows and 10 columns of prints We used CPLEX 8.100 to solve LP We used LINGO 6.0 to solve NLP We implemented the IASA heuristic in C All tests are run on an Intel Xeon 2.4GHz CPU

33. Experimental Results for SSDP Test Case # dice NLP-LingoLP-CPLEXIASA 40zCPU(s)40zCPU(s)40zCPU(s) 15250.3250.3250.0 26250.2250.2250.0 37211.4210.1210.0 481427.1146.7140.0 591440.7142.5140.0 610250.2254.3250.0 711184.1182.7180.0 81416294.11651.4160.0 916121236.41291.4120.0 10212012.220179.7200.0 Performance of IASA is much better

34. Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

35. What Floorplan is Good? 40 wafers needed for 40 copies 1 2 4 3 Min-area floorplan  high wafer cost 1 2 4 3 1 2 4 3 1 2 4 3 1 2 4 3

36. What Floorplan is Good? 40 wafers needed for 40 copies 1 2 4 3 Min-area floorplan  High wafer cost 1 2 4 3 1 2 4 3 1 2 4 3 1 2 4 3 Diagonal floorplan  Larger reticle  High wafer cost 1 2 4 3

37. What Floorplan is Good? 40 wafers needed for 40 copies 1 2 4 3 Min-area floorplan  high wafer cost 1 2 4 3 1 2 4 3 1 2 4 3 1 2 4 3 Diagonal floorplan  high mask cost 1 2 4 3 20 wafers needed for 40 copies Good floorplan 1 2 4 3 1 2 4 3 1 2 4 3 1 2 4 3 1 2 4 3

38. Reticle Design and Wafer Dicing Problem Given: n dice D i (i=1…n), reticle size Find: placement of dice within the reticle and a dicing plan To Minimize: w, the number of wafers used

39. Shelf Packing and Shifting Sort dice according to height

40. Shelf Packing and Shifting Sort dice according to height For all possible shelf widths, insert the dice into the shelves

41. Shelf Packing and Shifting Sort dice according to height For all possible shelf widths, insert the dice into the shelves Shift the dice to align them with the dice on other shelves and calculate z using IASA

42. Shelf Packing and Shifting Choose the placement with the max z Sort dice according to height For all possible shelf widths, insert the dice into the shelves Shift the dice to align them with the dice on other shelves and calculate z using IASA

43. Simulated Annealing Placement Get a shelf packing floorplan as the initial floorplan Calculate Objective Value =(1-α) area+ α(100-z) While (not converge and # of move < Move_Limit) { choose a uniform random number r make a random move according to r calculate δ = New Objective Value - Old Objective value If (δ <0) Accept the move Else Accept the move with probability exp(- (δ/T)) T=β T }

44. Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

45. Experimental Results for RDWDP Test Case # Die Die area GTMuchShelf+shiftSA+IASA 40zarea40zareaCPU40zareaCPU 11023118255162760.02828880 21822616285212530.225270783 31125215280162800.030294132 4920318221252240.030288118 51022612272252800.02526094 61522710285182380.018238226 71523414285152880.020285782 81423220285202880.020288152 91023120285162760.028288161 10202156304152550.0202601020 Total2277149275718726680.02442757 GTMuch is a commercial tool for MPW Improve wafer yield z by 37.7% compared with GTMuch Improve wafer yield z by 30.5% compared with shelf+shift

46. Solutions for Testcase 1 GTMuch Parquet Simulated annealingShelf+shift

47. Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

48. Conclusions We presented a MPW design flow We propose practical mathematical programming formulations and efficient heuristics, which can be extended to the case when margins are allowed By using the simulated annealing code, we can further improve wafer-dicing yield by 30.5% at the expense of an increase of area by 3.3%. The shelf packing and shifting algorithm can improve yield by 37.7% while reducing reticle area by 3.3% compared to GTMuch.

49. Future Research Validate proposed methods on industry testcases Extend the proposed algorithms to round wafer Multiple dicing plans

50. Thank you for your attention!