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L18 – VHDL for other counters and controllers. Other counters  More examples Gray Code counter Controlled counters  Up down counter  Ref: text Unit.

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Presentation on theme: "L18 – VHDL for other counters and controllers. Other counters  More examples Gray Code counter Controlled counters  Up down counter  Ref: text Unit."— Presentation transcript:

1 L18 – VHDL for other counters and controllers

2 Other counters  More examples Gray Code counter Controlled counters  Up down counter  Ref: text Unit 10, 17, 20 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU2

3 Gray code counter  What is Gray Code – it is a binary encoding that has only one bit transition from 0 to 1 or 1 to 0 in any successive count. 3 bit sequence – 3 bit Gray code count 000 – 001 – 011 – 010 – 110 – 111 – 101 – 100 – 000  How to generate? Actually quite easy and controlled 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU3

4 Gray Code generation  Start with the one bit  For 2 bit, put 1-bit code as lsb Precede by a 0 on 1 bit code Precede by a 1 on reflected 1 bit code Results in 2-bit count sequence  For n bit Gray Code Precede by a 0 on n-1 Gray bit code Precede by a 1 on reflected n-1 Gray bit code Results in n-bit count sequence 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU4

5 The HDL code for a 3 bit counter  The counter is a SED counter What is SED – Single Error Detecting SED will detect any single error that occurs in the architecture of the counter. This was for a specific purpose. Can easily be modified to be non SED. Only gives an indication (output signal) that error occurred.  The ENTITY ENTITY cnt3 IS PORT (clk : IN bit; cnt : OUT bit_vector(2 downto 0); dcnt : OUT bit_vector(2 downto 0); err : OUT bit); END cnt3; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU5

6 The declarative region ARCHITECTURE one OF cnt3 IS SIGNAL state,next_state : bit_vector(2 downto 0) := "000"; SIGNAL dstate,dnext_state : bit_vector(2 downto 0) := "111"; BEGIN  A binary encoded state machines  Two state machines are being specified  Each has state encoding of 3 bits 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU6

7 The F/F process  Note that both state machine Flip Flops are specified within the same process. This is acceptable. -- Latching logic specification PROCESS BEGIN WAIT UNTIL clk='1' AND clk'event; state <= next_state; dstate <= dnext_state; END PROCESS; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU7

8 Next state processes(2 of them)  --Next state logic for true logic  PROCESS (state)  BEGIN  CASE state IS  WHEN ("000") =>  next_state <= "001";  WHEN ("001") =>  next_state <= "011";  WHEN ("011") =>  next_state <= "010";  WHEN ("010") =>  next_state <= "110";  WHEN ("110") =>  next_state <= "111";  WHEN ("111") =>  next_state <= "101";  WHEN ("101") =>  next_state <= "100";  WHEN ("100") =>  next_state <= "000";  END CASE;  END PROCESS;  --Next state logic for dual logic  PROCESS (dstate)  BEGIN  CASE dstate IS  WHEN ("111") =>  dnext_state <= "110";  WHEN ("110") =>  dnext_state <= "100";  WHEN ("100") =>  dnext_state <= "101";  WHEN ("101") =>  dnext_state <= "001";  WHEN ("001") =>  dnext_state <= "000";  WHEN ("000") =>  dnext_state <= "010";  WHEN ("010") =>  dnext_state <= "011";  WHEN ("011") =>  dnext_state <= "111";  END CASE;  END PROCESS; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU8

9 The output process  Again quite simple --Assign outputs cnt <= state; dcnt <= dstate; err <= (state(0) XNOR dstate(0)) OR (state(1) XNOR dstate(1)) OR (state(2) XNOR dstate(2)); END one;  Note: As binary encoded output, output process can be a simple concurrent signal assignment. Also, generate the error signal output which is a direct Boolean function of the state encoding bits. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU9

10 Description of Quartis results  What would be expected? CLASS INPUT  Run through Quartis successfully 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU10

11 Quartis schematic result  The schematic  6 F/F (2 3-bit counters)  6 combinational elements with register  2 combinational elements with no register ?? Error signal generation 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU11

12 Up/Down Counter  An Up/Down counter is a controlled counter  Specification: Design a 3-bit counter that has an input c which indicates that the counter should be counting, an input r that resets the counter to 0 when asserted, and an input ud which says to count up when ud=1 and count down when ud=0. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU12

13 The HDL interface  THE ENTITY ENTITY cnt3ud IS PORT(clk,c,r,ud : IN BIT; cnt : OUT bit_vector(2 downto 0)); END cnt3ud;  This time there are several control signals in ENTITY 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU13

14 The declarative region  Start the ARCHITECTURE and state element process ARCHITECTURE one OF cnt3ud IS -- will use a binary encoded state SIGNAL state,next_state : bit_vector(2 downto 0) := "000"; BEGIN --state elements PROCESS BEGIN WAIT UNTIL clk='1' AND clk'event; state <= next_state; END PROCESS; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU14

15 Next state  This is where the input control affects the behavior of the machine. --next state process PROCESS (state,c,r,ud) BEGIN CASE state IS WHEN "000"=> IF (r='1') THEN next_state <= "000"; ELSIF (c='0') THEN next_state <= "000"; ELSIF (ud='1') THEN next_state <= "001"; ELSE next_state <= "111"; END IF; WHEN "001"=> IF (r='1') THEN next_state <= "000"; ELSIF (c='0') THEN next_state <= "001"; ELSIF (ud='1') THEN next_state <= "010"; ELSE next_state <= "000"; END IF; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU15

16 Next state continued WHEN "010"=> IF (r='1') THEN next_state <= "000"; ELSIF (c='0') THEN next_state <= "010"; ELSIF (ud='1') THEN next_state <= "011"; ELSE next_state <= "001"; END IF; WHEN "011"=> IF (r='1') THEN next_state <= "000"; ELSIF (c='0') THEN next_state <= "011"; ELSIF (ud='1') THEN next_state <= "100"; ELSE next_state <= "010"; END IF; WHEN "100"=> IF (r='1') THEN next_state <= "000"; ELSIF (c='0') THEN next_state <= "100"; ELSIF (ud='1') THEN next_state <= "101"; ELSE next_state <= "011"; END IF; WHEN "101"=> IF (r='1') THEN next_state <= "000"; ELSIF (c='0') THEN next_state <= "101"; ELSIF (ud='1') THEN next_state <= "110"; ELSE next_state <= "100"; END IF; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU16

17 The end of the next state process WHEN "110"=> IF (r='1') THEN next_state <= "000"; ELSIF (c='0') THEN next_state <= "110"; ELSIF (ud='1') THEN next_state <= "111"; ELSE next_state <= "101"; END IF; WHEN "111"=> IF (r='1') THEN next_state <= "000"; ELSIF (c='0') THEN next_state <= "111"; ELSIF (ud='1') THEN next_state <= "000"; ELSE next_state <= "110"; END IF; END CASE; END PROCESS; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU17

18 The output process  Again quite simple --output process cnt <= state; END one;  Before going off to synthesis the description needs to be simulated. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU18

19 The testbench  The start ENTITY testcnt3ud IS END testcnt3ud; ARCHITECTURE one OF testcnt3ud IS COMPONENT cnt3ud IS PORT(clk,c,r,ud : IN BIT; cnt : OUT bit_vector(2 downto 0)); END COMPONENT; FOR all : cnt3ud USE ENTITY work.cnt3ud(one); --declare hookup signals SIGNAL clk,c,r,ud : bit; SIGNAL cnt : bit_vector (2 downto 0); BEGIN 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU19

20 The common setup of clk  And wire in the component --set up clock - 50% duty cycle - 10 ns period clk <= NOT clk AFTER 5 ns; --instantiate component u1 : cnt3ud PORT MAP (clk,c,r,ud,cnt); 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU20

21 Now generate the controls --generate control signal stimulus PROCESS BEGIN --time 0 -- set up controls c <= '1'; -- count r <= '0'; -- don't reset ud <= '1'; -- count up WAIT for 100 ns; -- allow the system to count --reset the counter r <= '1'; WAIT for 10 ns; r <= '0'; -- start counting again WAIT for 50 ns; --start counting down ud <= '0'; WAIT for 100 ns; --flip back to counting up ud <= '1'; WAIT for 50 ns; --now hold count c <= '0'; WAIT for 50 ns; --now resume c <= '1'; WAIT for 50 ns; --should be done! WAIT; END PROCESS; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU21

22 The waveform  The first 120 ns – count then reset 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU22

23 The waveform  From 120 to 270 ns – counting down 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU23

24 The waveform  After 270 ns – suspend count 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU24

25 Enter into Quartis  And synthesize – this is a somewhat more complex design  3 registers  7 I/O pins  5 LUTs 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU25

26 Time for live demo  Demo of code in Modelsim  Demo of setup in Quartis  Probably want to take note of steps and editing shortcuts. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU26

27 Lecture summary  HDL for more complex counter HDL code Testbench  HDL for controlled counter Testbench needing control signal wave forms Simulation results Quartis results  Coming – TYPE std_logic 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU27

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