1. Binary Counters Module M10.3 Section 7.2

2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter

3. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter

4. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 11 1 1 Q2.D Q2.D = !Q2 & Q1 & Q0 # Q2 & !Q1 # Q2 & !Q0

5. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q1.D Q1.D = !Q1 & Q0 # Q1 & !Q0

6. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q0.D Q0.D = ! Q0

7. div8cnt.abl MODULE Div8Cnt TITLE 'Divide by 8 Counter, D. Hanna, 7/20/02' DECLARATIONS " INPUT PINS " PB PIN 10; " push-button switch (clock) " OUTPUT PINS " Q2..Q0 PIN 37,36,35 ISTYPE 'reg buffer'; " LED 6..8 Q = [Q2..Q0]; " 3-bit output vector [A,B,C,D,E,F,G,DP] PIN 15,18,23,21,19,14,17,24 ISTYPE 'com'; Segments = [A,B,C,D,E,F,G]; " 7-segment LED display

8. div8cnt.abl (cont’d) EQUATIONS Q.c = PB; Q2.d = !Q2 & Q1 & Q0 # Q2 & !Q1 # Q2 & !Q0; Q1.d = !Q1 & Q0 # Q1 & !Q0; Q0.d = !Q0; DP = PB; " decimal point @radix 16; truth_table ( Q -> Segments ) " 7-segment display 0 -> 7E; 1 -> 30; 2 -> 6D; 3 -> 79; 4 -> 33; 5 -> 5B; 6 -> 5F; 7 -> 70; END Div8Cnt Clock

9. Simulation File, div8cnt.si CUPL Simulation File

10. div8cnt.si CUPL Simulation File

11. CUPL Simulation Output File

12. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter

13. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D 3-Bit Down Counter

14. Q2 Q1 Q0 00011110 0 1 11 1 1 Q2.D Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D

15. 3-Bit Down Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q1.D Q1.D = !Q1 & !Q0 # Q1 & Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D

16. 3-Bit Down Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q0.D Q0.D = ! Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D

17. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter

18. Up-Down Counter Q0 Q1 Q2 clock UD UD = 0: count up UD = 1: count down

19. Up-Down Counter 1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0 UD Q2 Q1 Q0 Q2.D Q1.D Q0.D 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 UD Q2 Q1 Q0 Q2.D Q1.D Q0.D Up-CounterDown-Counter

20. UD Q2 Q1 Q0 00011110 00 01 11 10 Up-Down Counter Make Karnaugh maps for Q2.D, Q1.D, and Q0.D