1. UCLA DAC Tutorial 1997 EE 201A (Starting 2005, called EE 201B) Modeling and Optimization for VLSI Layout Instructor: Lei He Email: LHE@ee.ucla.edu

2. Chapter 9 n Transistor/gate sizing * n Buffer Insertion * Part of slides is provided by Prof. Sapatnekar from U. of Minnesota.

3. Transistor/Gate Sizing Optimization n Given:Logic network with or without cell library Find:Optimal size for each transistor/gate to minimize area or power, both under delay constraint Static sizing: based on timing analysis and consider all paths at once [Fishburn-Dunlop, ICCAD’85][Sapatnekar et al., TCAD’93] [Berkelaar-Jess, EDAC’90][Chen-Onodera-Tamaru, ICCAD’95] Dynamic sizing: based on timing simulation and consider paths activated by given patterns [Conn et al., ICCAD’96] n Transistor sizing versus gate sizing

4. The Transistor Sizing Problem Problem statement minimize Area(x) subject to Delay(x)  T spec or minimize Power(x) subject to Delay(x)  T spec Comb. Logic

5. Mathematical Background n n - dimensional space Any ordered n-tuple x = (x 1, x 2,..., x n ) can be thought of as a point in an n-dimensional space f(x 1,x 2,..., x n ) is a function on the n-dimensional space n Convex functions f(x) is a convex function if given any two points x a and x b, the line joining the two points lies on or above the function Nonconvex f: x f(x) xaxa xbxb xaxa xbxb x

6. Math Background (Contd.) n Convex functions in two dimensions f(x 1,x 2 ) = x 1 2 + x 2 2 Formally, f(x) is convex if f(  x a + [1 -  ] x b )   f(x a ) + [1 -  ] f(x b )0   1

7. Math Background (Contd.) n Convex sets A set S is a convex set if given any two points x a and x b in the set, the line joining the two points lies entirely within the set n Examples Shape of Shape of a Wyomingpizza n Nonconvex Sets Shape of CASilhouette of the Taj Mahal

8. Math Background (Contd.) n Mathematical characterization of a convex set S If x 1, x 2  S, then  x 1 + (1 -  ) x 2  S, for 0   1 n If f(x) is a convex function, f(x)  c is a convex set n An intersection of convex sets is a convex set x 1 x 2

9. Math Background (Contd.) n Convex programming problem minimize convex function f(x) such that  [f i (x)  c i ] n Global minimum value is unique! (Nonrigorous) explanation (from “The Handwaver’s Guide to the Galaxy”) x f(x) xaxa xbxb

10. Math Background (Contd. in English) A posynomial is like a  polynomial except all coefficients are positive exponents could be real numbers (positive or negative) n Are these posynomials? 6.023 x 1 1.23 + 4.56 x 1 3.4 x 2 7.89 x 3 -0.12 x 1 - 9.78 x 2 4.2 x 3 -9.1 (x 1 + 2 x 2 + 2 x 3 + 5)/x 1 + (x 3 + 2 x 4 + 3)/x 3 YES NO YES

11. n In any posynomial function f(x 1, x 2,..., x n ), substitutex i = exp(z i )to get F(z 1, z 2,..., z n ) n Then F(z 1, z 2,..., z n ) = convex function in (z 1,..., z n ) ! minimize (posynomial objective in x i ’s) s.t. (posynomial function in x i ’s) i  K for 1  i  m [x i = exp(z i )] minimize (convex objective) over a convex set Therefore, any local minimum is a global minimum! Math Background (Contd.)

12. Properties of Tr. Sizing under the Elmore Model n x is the set (vector) of transistor sizes minimize Area(x) subject to Delay(x)  T spec Area(x) =  i = 1 to n x i (posynomial!) Each path delay =  R C R  x i -1, C  x i  posynomial path delay function Delay(x)  T spec  Pathdelay(x)  T spec for all paths n Therefore, problem has a unique global min. value

13. TILOS™ (TImed LOgic Synthesis) n Philosophy Since min. value is unique, a simple method should find it! n Problem minimize Area(x) subject to Delay(x)  T spec n Strategy Set all transistors in the circuit to minimum size Find the critical path (largest delay path) Reduce delay of critical path, but with a minimal increase in the objective function value (TILOS™ is a registered trademark of Lucent Technologies)

14. TILOS (Contd.) minimize Area(x) subject to Delay(x)  T spec n Find  D/  A for all transistors on critical path n Bump up the size of transistor with the largest  D/  A x i  M x i + a (default: M = 1; a = 1 contact head width) Circuit Critical Path IN OUT

15. Sensitivity Computation n D(w) = K + R prev (C u. w) + R u. C / w n  D/  w = R prev. C u - R u. C / w 2 n Could minimize path delay by setting derivative to zero n Problem: may cause another path delay to become very high! R prev “1” w C

16. Why Isn’t This THE Perfect Solution? n Problems with interacting paths (1) Better to size A than to size all of B, C and D (2) If X-E is near-critical and A-D is critical, size A (not D) n False paths, layout considerations not incorporated n AND YET.. TILOS (the commercial tool) gives good solutions It has handled circuits with 250K transistors It has linear time performance with increasing circuit size A B C D X E

17. CONTRAST n Solves the convex optimization problem exactly n Uses an interior point method that is guaranteed to find the optimal solution n Can handle circuits with about a thousand transistors Delay spec. satisfied Optimal solution

18. (Convex) Polytopes n Polytope = n-dimensional convex polygon Half-space:a T x  b(a T x = b is a hyperplane) e.g. a 1 x 1 + a 2 x 2  b(in two dimensions) Polytope = intersection of half-spaces, i.e., a 1 T x  b 1 AND a 2 T x  b 2 AND a m T x  b m Represented as A x  b

19. Convex Optimization Algorithm (Vaidya) (1) Enclose solution within a polytope (invariant) Typically, take a “box” represented by w i  w MAX and w i  w MIN as the starting polytope. (2) Find center of polytope, w c (3) Does w c satisfy constraints (timing specs)? Take transistor widths corresponding to w c and perform a static timing analysis (4) Add a hyperplane through the center so that the solution lies entirely in one half-space Hyperplane equation depends on feasibility of w c

20. Half-space:  f (w c ). w   f (w c ). w c n If w c is feasible then f = objective function Find gradient of area function n If w c is infeasible then f = violated constraint Find gradient of critical path delay Equation of the New Half-Space wcwc

21. Illustrative Example f (w) = c, f decreasing solution S S S S w1w1 w2w2

22. Calculating the Polytope Center n Finding exact centroid is computationally expensive n Estimate center by minimizing log-barrier function F(x) = -  i=1 to m log (a i T x - b i ) Happy “coincidence”: F(x) is a convex function! n Physical meaning: maximize product of perpendicular distances to each hyperplane that defines the polytope

23. Linear Programming Methods n LP-based approaches Model gate delay as a piecewise linear function Parameters: transistor widths w n, w p fanout transistor widths input transition time Formulate problem as a linear program (LP) Use an efficient simplex package to solve LP Delay wnwn

24. Power-Delay Sizing minimize Power(w) subject to Delay(w)  T spec Area  A spec Each gate size  Minsize Power = dynamic power + short-circuit power

25. Dynamic Power n Dynamic Power Power required to charge/discharge capacitances P dynamic = C L V dd 2 f p T C L = load capacitance, f = clock frequency, p T = transition probability Posynomial function in w’s (if p T constant) Constitutes dominant part of power in a well-designed circuit Minimize dynamic power  minimize C L  minimize all transistor sizes! RIGHT? (Unfortunately not!) POST-IT

26. Short-Circuit Power n Short-circuit Power Power dissipated when a direct V dd -ground path exists Approximate formula by Veendrick (many assumptions) P short-ckt =  V dd -2V T ) 2  f p T  = transconductance,  = transition time Posynomial function in w’s (if p T const) Other (more accurate) models: table lookup, curve-fitting “Less than 10-20% of total power in a well-designed circuit” So what’s the catch? POST-IT

27. The Catch n Delay of gate A is large Therefore, the value of  for B, C,..., H is large Therefore short-circuit power for B, C,..., H is large Can be reduced by reducing the delay of A In other words, size A! n Tradeoff dynamic and short-circuit power! n Minpower  minsize A B C D X E F G H

28. begin Calculate p T 's ‘for minsized gates error <  ? end Solve gate sizing problem for current p T Calculate p T 's for new sizes error = ||old p T - new p T || Problem: inaccuracies in short-ckt. power model Solution Technique Yes No

29. Transistor/Gate Sizing [Borah-Owens-Irwin, ISLPD’95, TCAD’96] Optimal transistor size C I = int. cap

30. Power Optimal Sizes and Corresponding Power Savings

31. Power-Delay Optimization

32. Power, Delay and Power-Delay Curves

33. Power-Delay Optimal Transistor Sizing Algorithm n Power-Optimal initial sizing n Timing analysis n While exists path-delay > target-delay Power-delay optimal sizing critical path if path-delay > target-delay  upsize transistor with minimum power-delay slope if path-delay < target-delay  downsize transistor with minimum power-delay slope Incremental timing analysis

34. Effect of Transistor Sizing